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11. 发明授权

US07629822B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07629822B2
公开(公告)日：2009-12-08
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

12. 发明申请

US20090168565A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168565A1
公开(公告)日：2009-07-02
申请号：US12164984
申请日：2008-06-30
申请人： Kyoung-Nam KIM , Ho-Youb Cho
发明人： Kyoung-Nam KIM , Ho-Youb Cho
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C29/022 , G11C29/023
摘要： Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.
摘要翻译：半导体存储器件及其操作方法包括：辅助驱动器，被配置为响应于控制信号输出与读命令相对应的内部选通信号作为多个辅助选通信号，其中辅助驱动器绕过第一输出辅助选通信号和延迟以输出辅助选通信号中的其余的辅助选通信号和选通信号发生器，用于驱动辅助选通信号以输出延迟的辅助选通信号作为数据选通信号。

13. 发明授权

US07515482B2 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US07515482B2
公开(公告)日：2009-04-07
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

14. 发明申请

US20090063803A1 CIRCUIT FOR INITIALIZING A PIPE LATCH UNIT IN A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于在半导体存储器件中初始化管道单元的电路
公开(公告)号：US20090063803A1
公开(公告)日：2009-03-05
申请号：US12260298
申请日：2008-10-29
申请人： Kyoung-Nam KIM , Ho-Youb CHO
发明人： Kyoung-Nam KIM , Ho-Youb CHO
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

15. 发明申请

US20080165591A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080165591A1
公开(公告)日：2008-07-10
申请号：US11819803
申请日：2007-06-29
申请人： Kyoung-Nam Kim , Yoon-Jae Shin
发明人： Kyoung-Nam Kim , Yoon-Jae Shin
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/22 , G11C7/02 , G11C7/222
摘要： A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.
摘要翻译：半导体存储器件包括：调制控制器，用于产生用于控制频率调制操作的调制控制信号; 延迟锁定环（DLL）电路，用于执行延迟锁定操作以产生第一和第二DLL时钟并响应于调制控制信号输出调频DLL时钟; 以及数据选通信号发生器，用于输出调频DLL时钟作为数据选通信号。

16. 发明授权

US07368964B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07368964B2
公开(公告)日：2008-05-06
申请号：US11320847
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

17. 发明授权

US07345949B2 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US07345949B2
公开(公告)日：2008-03-18
申请号：US11325937
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Sang-Hee Kang
发明人： Kyoung-Nam Kim , Sang-Hee Kang
IPC分类号： G11C8/00
CPC分类号： G11C7/1072
摘要： A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.
摘要翻译：本发明的同步半导体存储器件包括：操作控制器，用于响应于列地址和列命令信号而输出列主动检测脉冲; 移位寄存器控制器，响应于列主动检测脉冲被激活，用于将时钟信号除以N，从而输出分频时钟信号，N是大于1的正整数; 多个移位寄存器串联连接并与分频时钟信号同步，其中每个移位寄存器将列活动检测脉冲发送到下一个移位寄存器; 以及列活动控制信号发生器，用于逻辑地组合移位寄存器的输出，从而生成列活动控制信号。

18. 发明授权

US07339847B2 BLEQ driving circuit in semiconductor memory device 有权
标题翻译： BLEQ驱动电路在半导体存储器件中
公开(公告)号：US07339847B2
公开(公告)日：2008-03-04
申请号：US11709745
申请日：2007-02-23
申请人： Kyoung-Nam Kim , Kang-Seol Lee
发明人： Kyoung-Nam Kim , Kang-Seol Lee
IPC分类号： G11C7/12
CPC分类号： G11C11/4094
摘要： A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply voltage, a BLEQ driver for generating the equalization signal by using the second boosted voltage in response to an equalization command and providing the equalization signal to a precharge unit, an equalizer and an I/O switch module. By using the second boosted voltage VPUP, which is lower than a first boosted voltage and higher than the supply voltage, as the equalization signal to be provided to gates of transistors for precharging a low power device to a precharge voltage level, it is possible to save current that a voltage pump consumes and satisfy a constant tRP.
摘要翻译：用于产生用于在半导体存储器件中执行预充电操作的均衡信号的位线均衡信号（BLEQ）驱动电路包括：第二升压电压发生器，用于通过泵送电源电压产生第二升压电压; BLEQ驱动器，用于产生均衡信号，并且将均衡信号提供给预充电单元，均衡器和I / O开关模块。通过使用低于第一升压电压并高于电源电压的第二升压电压VPUP作为要提供给用于将低功率器件预充电到预充电电压电平的晶体管的栅极的均衡信号，节省电压泵消耗并满足一定tRP的电流。

19. 发明授权

US07102938B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07102938B2
公开(公告)日：2006-09-05
申请号：US11102420
申请日：2005-04-08
申请人： Sang Hee Kang , Kyoung-Nam Kim
发明人： Sang Hee Kang , Kyoung-Nam Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/12 , G11C11/4094
摘要： An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要翻译：提供内部电压产生控制电路和使用其的内部电压产生电路。内部电压产生控制电路包括第一至第n锁存器和逻辑单元。第一锁存器作为输入信号接收在输入读/写命令之后产生的列有效脉冲信号，并且在预定时间期间锁存在启用时钟信号时接收的列活动脉冲信号的状态信息，以及然后输出锁存信息。第k个锁存器（2 <= k <= n）接收第k-1个锁存器的输出信号，并且锁存当时钟信号为时钟信号时接收到的第k-1个锁存器的输出信号的状态信息在预定时间内启用，然后输出锁存信息。逻辑单元执行列活动脉冲信号和n个锁存器的输出信号之间的逻辑运算，并输出内部电压产生控制信号。

20. 发明申请

US20050259499A1 Semiconductor memory device having a global data bus 有权
标题翻译：具有全局数据总线的半导体存储器件
公开(公告)号：US20050259499A1
公开(公告)日：2005-11-24
申请号：US11125447
申请日：2005-05-09
申请人： Kyoung-Nam Kim , Seok-Cheol Yoon
发明人： Kyoung-Nam Kim , Seok-Cheol Yoon
IPC分类号： G11C5/06 , G11C8/00 , G11C11/401 , G11C11/4093
CPC分类号： G11C5/063 , G11C8/10 , G11C11/4093
摘要： There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate it relying on the specific rule. The present invention proposes a scheme that classifies data transmission units corresponding to each bank into plural groups, each group having some continuous data transmission units, and makes bus lines of the global data bus to be arranged alternately for each group. In other words, the global data bus line arrangement scheme suggested by the present invention may be defined as grouped alternate arrangement scheme. In this case, the overlap interval between adjacent global data bus lines can be reduced largely and skew problem by lines can also be solved.
摘要翻译：提供半导体设计技术，特别是半导体存储器件中的全局数据总线的总线布置方法。根据本发明，可以不发生线偏斜，也可以在其发布时最小化。此外，在发行时，很容易根据具体规则进行补偿。本发明提出一种将每个存储体对应的数据传输单元分成多个组的方案，每个组具有一些连续的数据传输单元，并且使每个组交替布置全局数据总线的总线。换句话说，本发明提出的全局数据总线布置方案可以被定义为分组的替代安排方案。在这种情况下，相邻全局数据总线之间的重叠间隔可以大大减小，并且可以解决线上的倾斜问题。

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