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1. 发明授权

US07280418B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07280418B2
公开(公告)日：2007-10-09
申请号：US11469552
申请日：2006-09-01
申请人： Sang Hee Kang , Kyoung Nam Kim
发明人： Sang Hee Kang , Kyoung Nam Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/12 , G11C11/4094
摘要： An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k-1-th latch, and latches state information of the output signal of the k-1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要翻译：提供内部电压产生控制电路和使用其的内部电压产生电路。内部电压产生控制电路包括第一至第n锁存器和逻辑单元。第一锁存器作为输入信号接收在输入读/写命令之后产生的列有效脉冲信号，并且在预定时间期间锁存在启用时钟信号时接收的列活动脉冲信号的状态信息，以及然后输出锁存信息。第k个锁存器（2 <= k <= n）接收第k-1个锁存器的输出信号，并且锁存当时钟信号为时钟信号时接收到的第k-1个锁存器的输出信号的状态信息在预定时间内启用，然后输出锁存信息。逻辑单元执行列活动脉冲信号和n个锁存器的输出信号之间的逻辑运算，并输出内部电压产生控制信号。

2. 发明授权

US07102938B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07102938B2
公开(公告)日：2006-09-05
申请号：US11102420
申请日：2005-04-08
申请人： Sang Hee Kang , Kyoung-Nam Kim
发明人： Sang Hee Kang , Kyoung-Nam Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/12 , G11C11/4094
摘要： An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要翻译：提供内部电压产生控制电路和使用其的内部电压产生电路。内部电压产生控制电路包括第一至第n锁存器和逻辑单元。第一锁存器作为输入信号接收在输入读/写命令之后产生的列有效脉冲信号，并且在预定时间期间锁存在启用时钟信号时接收的列活动脉冲信号的状态信息，以及然后输出锁存信息。第k个锁存器（2 <= k <= n）接收第k-1个锁存器的输出信号，并且锁存当时钟信号为时钟信号时接收到的第k-1个锁存器的输出信号的状态信息在预定时间内启用，然后输出锁存信息。逻辑单元执行列活动脉冲信号和n个锁存器的输出信号之间的逻辑运算，并输出内部电压产生控制信号。

3. 发明申请

US20090299666A1 Fourier Transform-Based Phasor Estimation Method and Apparatus Capable of Eliminating Influence of Exponentially Decaying DC Offsets 有权
标题翻译：基于傅里叶变换的相量估计方法和能够消除指数衰减直流偏移影响的装置
公开(公告)号：US20090299666A1
公开(公告)日：2009-12-03
申请号：US12423223
申请日：2009-04-14
申请人： Sang Hee Kang , Dong Gyu Lee
发明人： Sang Hee Kang , Dong Gyu Lee
IPC分类号： G01R23/16 , G06F15/00
CPC分类号： G01R19/0015 , G01R15/18 , G01R31/024
摘要： Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the S influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal.
摘要翻译：这里公开了一种能够消除指数衰减DC偏移的S影响的基于傅里叶变换的相量估计方法和装置。根据本发明实施例的基于傅里叶变换的相量估计方法，对输入信号进行采样，将输入信号的一周期数据的采样分成至少两个采样组。对每个样本组执行离散傅里叶变换（DFT）。基于每个样本组上的DFT的结果计算输入信号中包括的DC偏移，并且使用计算的DC偏移计算由DC偏移引起的误差。通过从输入信号的DFT的结果中消除由DC偏移引起的计算出的误差来估计包括在输入信号中的基频分量的相量。

4. 发明申请

US20060120195A1 VOLTAGE GENERATION CONTROL CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE , CIRCUIT USING THE SAME AND METHOD THREREOF 有权
标题翻译：半导体存储器件中的电压产生控制电路，使用它的电路及其方法
公开(公告)号：US20060120195A1
公开(公告)日：2006-06-08
申请号：US10908534
申请日：2005-05-16
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/22 , G11C8/18
摘要： A voltage generation control circuit of a semiconductor memory device and method thereof are provided. A period tD, which is delayed for a given time after an internal row active time (tRAS) is secured since an active command is input, is set as an active operating period. An internal latency period, a burst length period and a latency delay period tDLT are set as a read/write operating period after a read/write command is input. A period tDRP delayed for a given time after a precharge command is input is set as a precharge operating period. In this state, a voltage generator is controlled to generate an active voltage only in the operating periods.
摘要翻译：提供半导体存储器件的电压产生控制电路及其方法。在输入有效命令之后，在内部行活动时间（tRAS）被确定之后延迟给定时间的周期tD被设置为活动操作周期。在输入读/写命令之后，将内部等待时间周期，突发长度周期和等待时间延迟周期tDLT设置为读/写操作周期。将预充电命令输入后的给定时间延迟的时段tDRP设定为预充电动作期间。在这种状态下，电压发生器被控制以仅在操作周期中产生有效电压。

5. 发明授权

US06879197B2 Apparatus for generating driving voltage for sense amplifier in a memory device 有权
标题翻译：用于在存储器件中产生读出放大器的驱动电压的装置
公开(公告)号：US06879197B2
公开(公告)日：2005-04-12
申请号：US10699722
申请日：2003-11-03
申请人： Chang Seok Kang , Sang Hee Kang
发明人： Chang Seok Kang , Sang Hee Kang
IPC分类号： G11C11/4091 , G11C7/06 , H03F3/45 , H03K3/02
CPC分类号： G11C7/06 , G11C2207/065
摘要： The apparatus for generating a driving voltage for a sense amplifier has at least voltage output means, and first and second core voltage step-up means. The voltage output means outputs a voltage for driving the sense amplifier to a node. Each of the first and second core voltage step-up means are connected between a power supply and the node. The first and second core voltage step-up means are turned on in sequence to elevate the voltage level of the node connected with the sense amplifier up to the level of the power supply. This enhances the performance of the sense amplifier as well as the execute detection amplification in a short time period. The first and second core voltage step-up means are turned on in sequence to elevate the core voltage as the driving voltage, reducing the power noise. Each core voltage step-up driver may be installed in each bank to reduce power consumption.
摘要翻译：用于产生用于感测放大器的驱动电压的装置至少具有电压输出装置，以及第一和第二电芯升压装置。电压输出装置将用于驱动读出放大器的电压输出到节点。第一和第二核心电压升压装置中的每一个连接在电源和节点之间。第一和第二核心电压升压装置依次导通，以将与感测放大器连接的节点的电压电平提升到电源的电平。这增强了读出放大器的性能以及在短时间内执行检测放大。第一和第二核心电压升压装置按顺序导通，以提高核心电压作为驱动电压，从而降低功率噪声。每个核心电压升压驱动器可以安装在每个存储体中以降低功耗。

6. 发明授权

US07602659B2 Memory device having shared fail-repairing circuit capable of repairing row or column fails in memory cell arrays of memory banks 有权
标题翻译：具有能够修复行或列的共享故障修复电路的存储器件在存储器组的存储单元阵列中失效
公开(公告)号：US07602659B2
公开(公告)日：2009-10-13
申请号：US10965550
申请日：2004-10-14
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： A memory device sharing a fail-repairing part is disclosed. The memory device has a plurality of banks that share a fuse and control unit for repairing a row fail or column fail in memory cell arrays in the respective banks. The memory device has reduced size and improved repair efficiency.
摘要翻译：公开了共享故障修复部件的存储器件。存储器件具有多个存储体，其共享用于修复各个存储体中的存储单元阵列中的行故障或列失败的熔丝和控制单元。存储器件具有减小的尺寸并提高修复效率。

7. 发明申请

US20050094344A1 Method of compensating for distorted secondary current of current transformer 失效
标题翻译：补偿电流互感器失真二次电流的方法
公开(公告)号：US20050094344A1
公开(公告)日：2005-05-05
申请号：US11010747
申请日：2004-12-13
申请人： Sang Hee Kang , Dong Gyu Lee , Seung Hyun , Yong Kang
发明人： Sang Hee Kang , Dong Gyu Lee , Seung Hyun , Yong Kang
IPC分类号： G01R15/18 , H02H1/04 , H02M3/335
CPC分类号： H02H1/046 , G01R15/183 , H02M2001/0009
摘要： Disclosed herein is a method of compensating for the distorted secondary current of a current transformer. The method includes steps (a), (b) and (c). At step (a), the saturated section of the current transformer is detected. At step (b), fault current generated during a fault in a power system is represented using an AutoRegressive (AR) model, with the fault current being assumed to be a combination of a Direct Current (DC) offset component, a fundamental wave component and a harmonic component. At step (c), normal secondary current during the saturation of the current transformer is estimated using a plurality of pieces of sampled secondary current data, based on the estimated coefficient of the AR model.
摘要翻译：本文公开了一种补偿电流互感器的失真次级电流的方法。该方法包括步骤（a），（b）和（c）。在步骤（a）中，检测电流互感器的饱和部分。在步骤（b）中，使用自动反馈（AR）模型来表示电力系统故障期间产生的故障电流，故障电流假定为直流（DC）偏移分量，基波分量和谐波分量。在步骤（c）中，基于AR模型的估计系数，使用多个采样次级电流数据估计电流互感器饱和期间的正常次级电流。

8. 发明授权

US07227794B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07227794B2
公开(公告)日：2007-06-05
申请号：US11155420
申请日：2005-06-17
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same. The internal voltage generation control circuit comprises a row active controller for enabling a first internal voltage generation control signal when a row active signal is enabled upon input of an active command and then disabling the first internal voltage generation control signal after the lapse of a first predetermined delay time if an RAS activation guarantee signal is enabled at a RAS active time after the first internal voltage generation control signal is enabled, an input/output controller for enabling a second internal voltage generation control signal when the row active signal and at least one of a data input signal and a data output signal are enabled and then disabling the second internal voltage generation control signal after the lapse of a second predetermined delay time if a row precharge signal is enabled or if the data input signal and data output signal are disabled, and a row precharge controller for enabling a third internal voltage generation control signal for a third predetermined delay time if the row precharge signal is enabled.
摘要翻译：这里公开了内部电压产生控制电路和使用该内部电压产生控制电路的内部电压产生电路。内部电压产生控制电路包括行有源控制器，用于当输入有效命令时使能行活动信号时能够实现第一内部电压产生控制信号，然后在经过第一预定值之后禁用第一内部电压产生控制信号如果RAS激活保证信号在第一内部电压产生控制信号被使能之后的RAS有效时间被使能的延迟时间，一个输入/输出控制器，用于当行活动信号和第二内部电压产生控制信号中的至少一个数据输入信号和数据输出信号被使能，然后如果行预充电信号被使能或数据输入信号和数据输出信号被禁止，则在经过第二预定延迟时间之后禁用第二内部电压产生控制信号，以及用于启用第三内部电压产生控制信号fo的行预充电控制器如果行预充电信号被使能，则为第三预定延迟时间。

9. 发明授权

US06747909B2 Decoding apparatus for semiconductor memory device, and enable method therefore 失效
标题翻译：因此，用于半导体存储器件的解码装置和使能方法
公开(公告)号：US06747909B2
公开(公告)日：2004-06-08
申请号：US10331746
申请日：2002-12-30
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1039 , G11C8/10 , G11C11/4087
摘要： The present disclosure discloses a decoding apparatus for a semiconductor memory device and an enable method therefor which can remove unnecessary delay between an address inputted to a decoder and a decoder control signal by enabling the decoder in response to the decoder control signal generated by combining an address latch control signal and an internal address according to an output signal from an address latch. The decoding apparatus for the semiconductor memory device includes an address latch to output first and second latch addresses and an internal address by latching an input address in response to an address latch control signal, an address transition detector to generate a decoder control signal by operating the address latch control signal and the internal address according to the first and second latch addresses, and a decoder enabled according to the decoder control signal.
摘要翻译：本公开公开了一种用于半导体存储器件的解码装置及其使能方法，其可以通过使解码器响应于通过组合地址而产生的解码器控制信号来消除输入到解码器的地址和解码器控制信号之间的不必要的延迟锁存控制信号和内部地址根据来自地址锁存器的输出信号。半导体存储器件的解码装置包括：地址锁存器，用于响应于地址锁存控制信号，通过锁存输入地址来输出第一和第二锁存器地址和内部地址;地址转换检测器，用于通过操作地址锁存控制信号和根据第一和第二锁存地址的内部地址，以及根据解码器控制信号使能的解码器。

10. 发明授权

US06731481B2 Relaying method for protecting transformers 失效
标题翻译：保护变压器的中继方法
公开(公告)号：US06731481B2
公开(公告)日：2004-05-04
申请号：US10001599
申请日：2001-10-23
申请人： Yong Cheol Kang , Sang Hee Kang , Byung Eun Lee , Jae Sung Yun , Seung Hun Ok
发明人： Yong Cheol Kang , Sang Hee Kang , Byung Eun Lee , Jae Sung Yun , Seung Hun Ok
IPC分类号： H02H704
CPC分类号： H02H7/0455 , H02H6/005
摘要： The present invention relates to a relaying method using the ratio of induced voltages or the ratio of flux linkage increments. The protective relaying method for power transformers with one or more phases includes the first step of obtaining primary and secondary voltages and currents of the transformer; the second step of calculating induced voltages, induced voltage differences, ratio of primary and secondary induced voltages, or ratio of primary and secondary induced voltage differences from the currents and the voltages; the third step of calculating at least one predetermined decision parameter derived from at least one predetermined equation; the fourth step of deciding whether an internal winding fault occurs by comparing the decision parameter to the induced voltages, the induced voltage differences, the ratio of primary and secondary induced voltages, or the ratio of primary and secondary induced voltage differences.
摘要翻译：本发明涉及使用感应电压比或磁链增量比的中继方法。具有一个或多个相的电力变压器的保护继电方法包括获得变压器的初级和次级电压和电流的第一步骤; 计算感应电压，感应电压差，初级和次级感应电压的比率或初级和次级感应电压差与电流和电压的比率的第二步; 计算从至少一个预定方程导出的至少一个预定决定参数的第三步骤; 通过将判定参数与感应电压，感应电压差，初级和次级感应电压的比率或初级和次级感应电压差的比值进行比较来决定是否发生内部绕组故障。

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