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11. 发明授权

US6004865A Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator 失效
标题翻译：制造具有形成在绝缘体上的单晶半导体膜的多层结构的方法
公开(公告)号：US6004865A
公开(公告)日：1999-12-21
申请号：US612647
申请日：1996-03-08
申请人： Masatada Horiuchi , Takahiro Onai , Katsuyoshi Washio
发明人： Masatada Horiuchi , Takahiro Onai , Katsuyoshi Washio
IPC分类号： H01L21/84 , H01L27/12 , H01L21/331 , H01L21/20 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , Y10S438/977
摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.
摘要翻译：公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。SOI 通过直接接合技术形成衬底，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

12. 发明授权

US5324983A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5324983A
公开(公告)日：1994-06-28
申请号：US902592
申请日：1992-06-22
申请人： Takahiro Onai , Takeo Shiba , Tohru Nakamura , Yoichi Tamaki , Katsuyoshi Washio , Kazuhiro Ohnishi , Masayoshi Saitoh
发明人： Takahiro Onai , Takeo Shiba , Tohru Nakamura , Yoichi Tamaki , Katsuyoshi Washio , Kazuhiro Ohnishi , Masayoshi Saitoh
IPC分类号： H01L21/28 , H01L21/331 , H01L29/423 , H01L29/73 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/00
CPC分类号： H01L29/66272 , H01L29/42304
摘要： A first region of a first conductivity type is formed in the surface of a semiconductor body, and second and third regions of a second conductivity type are formed on and under, respectively, of the first region. An electrode region formed on a first insulating film formed on the semiconductor body is connected electrically to the first region. The electrode region is defined as having an elongated first part an upper surface of which is connected to an electrode, and having a second, different part which has a substantially constant width and which width is substantially equal to the thickness of the first portion of the electrode region. A metal silicide film is formed over the upper surface of the first portion of the electrode region. The first, second and third regions can be base, emitter and collector regions, respectively, of a bipolar transistor formed in an island region of an epitaxially grown layer on a semiconductor substrate.
摘要翻译：第一导电类型的第一区域形成在半导体本体的表面中，并且第二导电类型的第二和第三区域分别形成在第一区域的上下。形成在形成在半导体主体上的第一绝缘膜上的电极区域与第一区域电连接。电极区域被限定为具有细长的第一部分，其上表面连接到电极，并且具有第二不同部分，其具有基本恒定的宽度，并且该宽度基本上等于第一部分的厚度电极区域。在电极区域的第一部分的上表面上形成金属硅化物膜。第一，第二和第三区域可以分别是形成在半导体衬底上的外延生长层的岛区中的双极晶体管的基极，发射极和集电极区域。

13. 发明授权

US08711523B2 Stacked magnetoresistance device responsive to a magnetic field generally perpendicular to a side face running along a channel of the device 失效
标题翻译：堆叠的磁阻器件响应于通常垂直于沿着器件通道运行的侧面的磁场
公开(公告)号：US08711523B2
公开(公告)日：2014-04-29
申请号：US12915648
申请日：2010-10-29
申请人： Susumu Ogawa , David Williams , Hiroshi Fukuda , Katsuyoshi Washio
发明人： Susumu Ogawa , David Williams , Hiroshi Fukuda , Katsuyoshi Washio
IPC分类号： G11B5/33
CPC分类号： H01L43/08 , B82Y25/00 , G01R33/093 , G01R33/095 , G11B5/3993 , H01L43/12
摘要： A magnetoresistance device comprises a substrate, an elongate semiconductor channel extending in a first direction and at least two conductive leads providing a set of contacts to the channel. The device may comprise an optional semiconductor shunt in contact with the channel. The optional shunt, channel and set of contacts are stacked relative to the substrate in a second direction which is perpendicular to the first direction and the surface of the substrate. The device has a side face running along the channel. The device is responsive to a magnetic field generally perpendicular to the side face.
摘要翻译：磁阻器件包括衬底，沿第一方向延伸的细长半导体沟道和至少两个导电引线，提供一组通道的触点。该装置可以包括与通道接触的可选的半导体分流器。可选的分流器，沟道和触点组在垂直于第一方向和衬底的表面的第二方向上相对于衬底堆叠。该设备具有沿着通道运行的侧面。该装置响应于一般垂直于侧面的磁场。

14. 发明授权

US07842973B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07842973B2
公开(公告)日：2010-11-30
申请号：US11485287
申请日：2006-07-13
申请人： Makoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
发明人： Makoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , Y10S438/936
摘要： A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier generated upon increase of the collector current and enabling satisfactory transistor operation at high current.
摘要翻译：一种半导体器件及其制造方法，其能够在保持高耐受电压的同时避免在导带中产生阻挡层并能够在高电流下进行高速晶体管的操作，以及其制造方法，其中，集电体由禁带宽度窄于半导体衬底的材料形成，禁带从发射极侧向集电极侧逐步且连续地增加的区域设置在基体的内部，禁带在基极集电体界面的宽度被设计为大于基极中的最小禁带宽度，由此集电极侧的基底边缘处的禁带宽度可以更接近半导体的禁带宽度衬底，同时充分保持发射极基极附近的杂质效应，从而能够降低高度在集电极电流增加时产生能量势垒，并且能够在高电流下令人满意的晶体管工作。

15. 发明授权

US07071500B2 Semiconductor device and manufacturing method for the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07071500B2
公开(公告)日：2006-07-04
申请号：US10866673
申请日：2004-06-15
申请人： Makoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
发明人： Makoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
IPC分类号： H01L31/072
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/41708 , H01L29/732
摘要： A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.
摘要翻译：一种双极半导体器件，包括在其外周的一部分上覆盖有绝缘膜并且具有在上方向和水平方向上延伸的形状的集电极层，在集电层和绝缘膜之间形成间隙，以及还包括设置在集电极层上的基极层和发射极层，以及半导体器件的制造方法。由于集电体层的一部分在上下方向和水平方向上延伸，所以可以消除外部集电极区域，能够减少归因于集电体的本征部分的寄生电容和集电极电容，因此，可以构成能够以降低的消耗功率进行高速运转的双极型晶体管。

16. 发明授权

US06974977B2 Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US06974977B2
公开(公告)日：2005-12-13
申请号：US10457428
申请日：2003-06-10
申请人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
发明人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
IPC分类号： H01L29/72 , G02B6/42 , H01L21/331 , H01L29/737 , H03F3/45
CPC分类号： H01L29/66242 , G02B6/4251 , G02B6/4274 , H01L29/7375 , H01L29/7378 , H03F3/45085 , H03F3/45089 , H03F2200/372 , H03F2203/45311 , H03F2203/45574 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
摘要翻译：提供了具有高可靠性和高增益的双极晶体管，并且特别适用于高速运行。双极晶体管以高精度工作，即使在集电极电压变化时也不会对集电极电流产生实质性的变化。与传统的集电极电流双极晶体管相比，它具有较小的变化，同时确保了高速性能和高增益。在一个示例中，基极区域中的带隙小于发射极和集电极区域中的带隙。带隙在与发射极区域的结点附近是恒定的，并且朝着与集电极区域的结点减小。单晶硅/锗通常用于基极区域。

17. 发明授权

US06815707B2 Field-effect type semiconductor device for power amplifier 有权
标题翻译：功率放大器的场效应半导体器件
公开(公告)号：US06815707B2
公开(公告)日：2004-11-09
申请号：US10259396
申请日：2002-09-30
申请人： Nobuyuki Sugii , Masatoshi Morikawa , Isao Yoshida , Katsuyoshi Washio
发明人： Nobuyuki Sugii , Masatoshi Morikawa , Isao Yoshida , Katsuyoshi Washio
IPC分类号： H01L2904
CPC分类号： H01L29/66659 , H01L29/1045 , H01L29/1087 , H01L29/165 , H01L29/7835 , H03F3/601 , Y10S438/933
摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
摘要翻译：在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层高杂质浓度或底物。

18. 发明授权

US06723541B2 Method of producing semiconductor device and semiconductor substrate 失效
标题翻译：半导体器件和半导体衬底的制造方法
公开(公告)号：US06723541B2
公开(公告)日：2004-04-20
申请号：US10163312
申请日：2002-06-07
申请人： Nobuyuki Sugii , Shinya Yamaguchi , Katsuyoshi Washio
发明人： Nobuyuki Sugii , Shinya Yamaguchi , Katsuyoshi Washio
IPC分类号： H01L2100
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/02667 , H01L21/3226 , H01L21/76251 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.
摘要翻译：一种制造用于半导体衬底的应变松弛Si-Ge虚拟衬底的方法，该半导体衬底是平面的，并且具有较少的缺陷，用于提高场效应半导体器件的性能，该方法包括覆盖形成在SOI上的Si-Ge层具有绝缘层的衬底以防止Ge的蒸发，在高于由Si-Ge层的锗含量确定的固相线曲线温度的部分熔融状态下加热硅和锗的混合层，并将锗扩散到 Si层，从而使熔融的Si-Ge层固化，得到应变松弛的Si-Ge虚拟基板。

19. 发明授权

US06600178B1 Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US06600178B1
公开(公告)日：2003-07-29
申请号：US09599741
申请日：2000-06-23
申请人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
发明人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
IPC分类号： H01L29737
CPC分类号： H01L29/66242 , G02B6/4251 , G02B6/4274 , H01L29/7375 , H01L29/7378 , H03F3/45085 , H03F3/45089 , H03F2200/372 , H03F2203/45311 , H03F2203/45574 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
摘要翻译：提供了具有高可靠性和高增益的双极晶体管，并且特别适用于高速运行。双极晶体管以高精度工作，即使在集电极电压变化时也不会对集电极电流产生实质性的变化。与传统的集电极电流双极晶体管相比，它具有较小的变化，同时确保了高速性能和高增益。在一个示例中，基极区域中的带隙小于发射极和集电极区域中的带隙。带隙在与发射极区域的结点附近是恒定的，并且朝着与集电极区域的结点减小。单晶硅/锗通常用于基极区域。

20. 发明授权

US06521974B1 Bipolar transistor and manufacturing method thereof 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US06521974B1
公开(公告)日：2003-02-18
申请号：US09689800
申请日：2000-10-13
申请人： Katsuya Oda , Eiji Ohue , Masao Kondo , Katsuyoshi Washio , Masamichi Tanabe , Hiromi Shimamoto
发明人： Katsuya Oda , Eiji Ohue , Masao Kondo , Katsuyoshi Washio , Masamichi Tanabe , Hiromi Shimamoto
IPC分类号： H01L2970
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si—Ge and a base leading-out electrode are connected via a link base made of polycrystal Si—Ge by doping at high concentration, further, a part immediately under the intrinsic base has the same conductive type as that of a collector and in a peripheral part, a single crystal Si—Ge layer having the same conductive type as that of a base is provided between the intrinsic base and a collector layer. Hereby, the reduction of the resistance of the link base between the intrinsic base and the base leading-out electrode and the reduction of capacitance between the collector and the base are simultaneously realized, and a self-aligned bipolar transistor wherein capacitance between an emitter and the base and capacitance between the collector and the base are respectively small, power consumption is small and high speed operation is enabled is acquired.
摘要翻译：根据本发明的双极晶体管具有以下结构：由单晶Si-Ge构成的本征基极和基极引出电极通过高浓度掺杂的由多晶Si-Ge制成的连接基底连接，此外，在本征基底之下的部分具有与集电体相同的导电类型，并且在外围部分中，在本征基极和集电极层之间设置具有与基底相同的导电类型的单晶Si-Ge层。因此，同时实现本征基极与基极引出电极之间的基极的电阻的降低和集电极与基极之间的电容的减小，以及自对准双极晶体管，其中发射极和集电极和基极之间的基极和电容分别小，功耗小，获得高速运行。

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