专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08329532B2 Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权
公开(公告)号：US08329532B2
公开(公告)日：2012-12-11
申请号：US13314595
申请日：2011-12-08
申请人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
发明人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
IPC分类号： H01L21/8238
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

12. 发明授权

US08115274B2 Fuse structure and method for manufacturing same 有权
标题翻译：保险丝结构及其制造方法
公开(公告)号：US08115274B2
公开(公告)日：2012-02-14
申请号：US11855004
申请日：2007-09-13
申请人： Josef Boeck , Herbert Knapp , Wolfgang Liebl , Herbert Schaefer
发明人： Josef Boeck , Herbert Knapp , Wolfgang Liebl , Herbert Schaefer
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.
摘要翻译：保险丝结构包括衬底，布置成更接近第一芯片表面的熔丝导电迹线，而不是靠近第二芯片表面的第二芯片表面;衬底上的金属化层，设置在熔丝导电迹线的背离所述第一芯片表面以及布置在所述熔丝导电迹线和所述金属化层之间并且包括多个不同材料的阻挡层的平面势垒层叠组件，其中所述熔丝导电迹线，所述金属化层和所述阻挡层多层组件被布置成使得当切割所述熔丝导电迹线和所述阻挡层多层组件，所述金属化层的第一区域与所述金属化层的第二区域电隔离。

13. 发明授权

US08067290B2 Bipolar transistor with base-collector-isolation without dielectric 有权
标题翻译：双极晶体管，具有基极集电绝缘无绝缘
公开(公告)号：US08067290B2
公开(公告)日：2011-11-29
申请号：US12642188
申请日：2009-12-18
申请人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
发明人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
IPC分类号： H01L21/331
CPC分类号： H01L29/7322 , H01L29/0649 , H01L29/0821 , H01L29/66272
摘要： The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).
摘要翻译：所公开的发明提供了一种用于制造双极晶体管的方法，该双极晶体管具有包含在通过一个或多个填充有低介电常数气体的隔离空腔（例如，气隙）与上覆基极区域分离的半导体主体内的集电极区域。特别地，在集电极区域上沉积多层基极集电极电介质膜。在多层电介质膜上形成基极区，并形成一个或多个基极连接区域。在多个各向同性蚀刻工艺期间选择性地蚀刻多层电介质膜，以允许在基底连接区域和收集区域之间形成一个或多个隔离区域，其中一个或多个隔离区域包括填充有具有低介电常数（如空气）。所得的双极晶体管具有降低的基极 - 集电极电容，从而允许改进的频率特性（例如，较高的最大频率运行）。

14. 发明申请

US20100187657A1 BIPOLAR TRANSISTOR WITH BASE-COLLECTOR-ISOLATION WITHOUT DIELECTRIC 有权
标题翻译：具有无电介质的基础收集器隔离的双极晶体管
公开(公告)号：US20100187657A1
公开(公告)日：2010-07-29
申请号：US12642188
申请日：2009-12-18
申请人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
发明人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/7322 , H01L29/0649 , H01L29/0821 , H01L29/66272
摘要： The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).
摘要翻译：所公开的发明提供了一种用于制造双极晶体管的方法，该双极晶体管具有包含在通过一个或多个填充有低介电常数气体的隔离空腔（例如，气隙）与上覆基极区域分离的半导体主体内的集电极区域。特别地，在集电极区域上沉积多层基极集电极电介质膜。在多层电介质膜上形成基极区，并形成一个或多个基极连接区域。在多个各向同性蚀刻工艺期间选择性地蚀刻多层电介质膜，以允许在基底连接区域和收集区域之间形成一个或多个隔离区域，其中一个或多个隔离区域包括填充有具有低介电常数（如空气）。所得的双极晶体管具有降低的基极 - 集电极电容，从而允许改进的频率特性（例如，更高的最大频率运行）。

15. 发明申请

US20090261327A1 PROCESS FOR THE SIMULTANEOUS DEPOSITION OF CRYSTALLINE AND AMORPHOUS LAYERS WITH DOPING 有权
标题翻译：晶体和非晶层同时沉积的方法
公开(公告)号：US20090261327A1
公开(公告)日：2009-10-22
申请号：US12106667
申请日：2008-04-21
申请人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
发明人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
IPC分类号： H01L27/00 , H01L21/62
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
摘要翻译：本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。沉积包括形成两个或更多个子层。可以为每个单独的子层改变工艺参数以优化沉积特性。

16. 发明申请

US20080067627A1 Fuse Structure and Method for Manufacturing Same 有权
标题翻译：保险丝结构及其制造方法相同
公开(公告)号：US20080067627A1
公开(公告)日：2008-03-20
申请号：US11855004
申请日：2007-09-13
申请人： Josef Boeck , Herbert Knapp , Wolfgang Liebl , Herbert Schaefer
发明人： Josef Boeck , Herbert Knapp , Wolfgang Liebl , Herbert Schaefer
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.
摘要翻译：保险丝结构包括衬底，布置成更接近第一芯片表面的熔丝导电迹线，而不是靠近第二芯片表面的第二芯片表面;衬底上的金属化层，设置在熔丝导电迹线的背离所述第一芯片表面以及布置在所述熔丝导电迹线和所述金属化层之间并且包括多个不同材料的阻挡层的平面势垒层叠组件，其中所述熔丝导电迹线，所述金属化层和所述阻挡层多层组件被布置成使得当切割所述熔丝导电迹线和所述阻挡层多层组件，所述金属化层的第一区域与所述金属化层的第二区域电隔离。

17. 发明授权

US5218223A Opto-electronic semiconductor component 失效
标题翻译： OPTO-ELECTRONIC SEMICONDUCTOR COMPONENT
公开(公告)号：US5218223A
公开(公告)日：1993-06-08
申请号：US524442
申请日：1990-05-17
申请人： Werner Spaeth , Wolf Jakowetz , Herbert Schaefer , Michael Besand , Karl Osojnik
发明人： Werner Spaeth , Wolf Jakowetz , Herbert Schaefer , Michael Besand , Karl Osojnik
IPC分类号： H01L31/0232 , H01L31/0352 , H01L31/10 , H01L33/20 , H01L33/44 , H01L33/46
CPC分类号： H01L33/20 , H01L31/0232 , H01L31/035281 , H01L33/44 , H01L33/46 , Y02E10/50
摘要： An opto-electronic semiconductor component having a light transmission or receiving property including a light emitting or detecting active zone lying parallel to the principle surface of the semiconductor crystal is formed so that it detects or emits light directed parallel to the active zone with high efficiency. This enables the component to be hybridize with other electrical, electro-optical or optical elements in a single plane. At least one lateral surface of the semiconductor crystal is inclined at an angle to the principle surface of the component such that light directed into or from the crystal in a direction parallel to the active zone experiences deflection by refraction or reflection toward or away from the active zone.
摘要翻译：形成具有包含平行于半导体晶体的主面的发光或检测有源区的光透射或接收特性的光电子半导体元件，以便以高效率检测或发射平行于活性区的光。这使得组件能够与单个平面中的其它电，电光或光学元件杂交。半导体晶体的至少一个侧表面与部件的主要表面成一角度倾斜，使得在平行于有源区域的方向上导入晶体或从晶体引入的光经由折射或反射朝向或远离有源区域而发生偏转区。

18. 发明授权

US07872349B2 Integrated coolant circuit arrangement, operating method and production method 有权
标题翻译：集成冷却液回路装置，操作方法及生产方法
公开(公告)号：US07872349B2
公开(公告)日：2011-01-18
申请号：US11324789
申请日：2006-01-03
申请人： Volker Lehmann , Reinhard Stengl , Herbert Schaefer
发明人： Volker Lehmann , Reinhard Stengl , Herbert Schaefer
IPC分类号： H01L23/473
CPC分类号： H01L23/473 , H01L21/30604 , H01L21/3063 , H01L23/427 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.
摘要翻译：提供一种集成电路装置及其制造方法。至少一个集成电子部件布置在基板的主要区域。该部件布置在基板中，或者通过电绝缘区域与基板隔离。主通道形成在基板上并且沿着主区域布置。每个主通道相对于纵向轴线横向地完全被基底包围。横向通道相对于主通道横向布置。每个横向通道打开至少一个主通道。超过十个横向通道进入主通道。

19. 发明授权

US07064360B2 Bipolar transistor and method for fabricating it 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07064360B2
公开(公告)日：2006-06-20
申请号：US10470816
申请日：2002-02-04
申请人： Martin Franosch , Thomas Meister , Herbert Schaefer , Reinhard Stengl
发明人： Martin Franosch , Thomas Meister , Herbert Schaefer , Reinhard Stengl
IPC分类号： H01L31/0328
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.
摘要翻译：提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。此外，很大程度上避免了与点缺陷相关的困难。

20. 发明授权

US5945704A Trench capacitor with epi buried layer 失效
标题翻译：带Epi埋层的沟槽电容器
公开(公告)号：US5945704A
公开(公告)日：1999-08-31
申请号：US105945
申请日：1998-06-26
申请人： Martin Schrems , Jack Mandelman , Joachim Hoepfner , Herbert Schaefer , Reinhard Stengl
发明人： Martin Schrems , Jack Mandelman , Joachim Hoepfner , Herbert Schaefer , Reinhard Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/94 , H01L31/119 , H01L27/76
CPC分类号： H01L27/10861 , H01L29/945
摘要： A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
摘要翻译：具有沟槽下部的外延层的沟槽式电容器。外延层用作沟槽电容器的掩埋板。扩散区域围绕沟槽的下部以增强外延层的掺杂剂浓度。扩散区域通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式