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11. 发明授权

US07012299B2 Storage layer optimization of a nonvolatile memory device 有权
标题翻译：非易失性存储器件的存储层优化
公开(公告)号：US07012299B2
公开(公告)日：2006-03-14
申请号：US10668693
申请日：2003-09-23
申请人： Maitreyee Mahajani , Andrew J. Walker , En-Hsing Chen
发明人： Maitreyee Mahajani , Andrew J. Walker , En-Hsing Chen
IPC分类号： H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792
摘要： The traditional nitride-only charge storage layer of a SONOS device is replaced by a multifilm charge storage layer comprising more than one dielectric material. Examples of such a multifilm charge storage layer are alternating layers of silicon nitride and silicon dioxide, or alternating layers of silicon nitride and aluminum oxide. The use of more than one material introduces additional barriers to migration of charge carriers within the charge storage layer, and improves both endurance and retention of a SONOS-type memory cell comprising such a charge storage layer.
摘要翻译： SONOS器件的传统的仅含氮化物的电荷存储层被包含多于一种电介质材料的多层电荷存储层所替代。这种多重电荷存储层的实例是氮化硅和二氧化硅的交替层，或氮化硅和氧化铝的交替层。使用多于一种材料引入电荷载流子在电荷存储层内迁移的附加障碍，并且改善了包括这种电荷存储层的SONOS型存储单元的耐久性和保留性。

12. 发明授权

US06888750B2 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication 有权
标题翻译： SOI和复合半导体衬底上的非易失性存储器及其制造方法
公开(公告)号：US06888750B2
公开(公告)日：2005-05-03
申请号：US09927642
申请日：2001-08-13
申请人： Andrew J. Walker , Mark G. Johnson , N. Johan Knall , Igor G. Kouznetsov , Christopher J. Petti
发明人： Andrew J. Walker , Mark G. Johnson , N. Johan Knall , Igor G. Kouznetsov , Christopher J. Petti
IPC分类号： G11C16/04 , H01L21/77 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/06 , H01L27/102 , H01L27/115 , G11C5/02 , G11C16/00
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/822 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11578
摘要： A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.
摘要翻译：提供非易失性存储器阵列。阵列包括非易失性存储器件阵列，至少一个驱动器电路和衬底。至少一个驱动电路不位于大块单晶硅衬底中。至少一个驱动电路可以位于绝缘体上硅衬底或化合物半导体衬底中。

13. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

14. 发明申请

US20110021019A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20110021019A1
公开(公告)日：2011-01-27
申请号：US12897696
申请日：2010-10-04
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

15. 发明授权

US07777268B2 Dual-gate device 有权
标题翻译：双门装置
公开(公告)号：US07777268B2
公开(公告)日：2010-08-17
申请号：US11548231
申请日：2006-10-10
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/786
CPC分类号： H01L29/792 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/42352
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.
摘要翻译：公开了一种具有双栅极存储单元的存储电路及其制造方法。双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。半导体层的厚度使得与存取装置的栅电极和存储装置之间的电相互作用相关的灵敏度参数小于预定值。双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。在这样的阵列中，在NAND串中的附近的存储器件的编程期间，在不被编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动，存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

16. 发明申请

US20100140679A1 STACKED DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF 审中-公开
标题翻译：具有抗源漏区的堆叠双栅极NMOS器件及其制造方法
公开(公告)号：US20100140679A1
公开(公告)日：2010-06-10
申请号：US12329477
申请日：2008-12-05
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/788
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11551 , H01L27/11597 , H01L29/66833 , H01L29/792
摘要： A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in stacked memory devices because antimony can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices in a stacked memory device with well-controlled channel lengths may be achieved.
摘要翻译：三维存储器结构包括多层存储器件，每个存储器件包括双栅极器件。双栅极器件包括在第一栅极结构和第二栅极结构之间的有源层。每个栅极结构通过介电层与有源层隔离，并且位于由通过注入锑离子形成的间隔扩散区限定的有源层中的半导体或沟道区的上方。锑掺杂扩散区特别适用于堆叠式存储器件，因为锑可以在低于900℃的温度下被注入和激活，并且即使在制造过程中经过许多热步骤之后也不会发生注入的锑离子的移动。结果，可以实现具有良好控制的通道长度的堆叠存储器件中的双栅极器件。

17. 发明申请

US20090090913A1 DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) 审中-公开
标题翻译：具有多通道单元（MLC）通道结晶的双门存储器件
公开(公告)号：US20090090913A1
公开(公告)日：2009-04-09
申请号：US11866899
申请日：2007-10-03
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L29/66825 , B82Y10/00 , G11C11/5621 , G11C2211/5611 , G11C2216/06 , H01L21/02532 , H01L21/02667 , H01L21/02686 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth.
摘要翻译：提供了具有存储晶体管和存取晶体管的方法和双栅极存储器件，以允许将多个位存储在双栅极存储器件中。存储晶体管和存取晶体管各自具有在从非晶半导体材料结晶的迁移率增强材料中形成的沟道区。非晶半导体材料可以包括例如硅。移动性增强可以通过以下方式实现：（a）准分子激光退火; （b）横向结晶; （c）金属诱导的横向结晶; （d）激光退火和金属诱导横向结晶步骤的组合; 或（e）固相外延生长。

18. 发明授权

US07495337B2 Dual-gate device and method 有权
标题翻译：双栅极器件及方法
公开(公告)号：US07495337B2
公开(公告)日：2009-02-24
申请号：US11671859
申请日：2007-02-06
申请人： Andrew J. Walker , Maitreyee Mahajani
发明人： Andrew J. Walker , Maitreyee Mahajani
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1203 , G11C16/0483 , H01L21/84 , H01L27/115 , H01L27/11517 , H01L27/11568 , H01L29/4908 , H01L29/66742 , H01L29/78645 , H01L29/78648 , Y10S438/951
摘要： A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.
摘要翻译：双栅极器件形成在半导体衬底上并与半导体衬底绝缘，半导体衬底可以包括可以互连到双栅极器件的附加功能电路。双栅极器件包括形成在公共有源半导体区域的相对表面上的两个半导体器件，其提供足以将半导体器件与静电相互作用隔离的厚度和材料。在一个实施例中，半导体器件之一包括诸如ONO层的电荷存储层。这种双栅极器件适用于非易失性存储器阵列。

19. 发明申请

US20080084745A1 DUAL-GATE DEVICE AND METHOD 有权
公开(公告)号：US20080084745A1
公开(公告)日：2008-04-10
申请号：US11548231
申请日：2006-10-10
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/788 , G11C11/34 , H01L21/336
CPC分类号： H01L29/792 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/42352
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

20. 发明授权

US07233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07233522B2
公开(公告)日：2007-06-19
申请号：US10729831
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

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