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11. 发明申请

US20120210073A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120210073A1
公开(公告)日：2012-08-16
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

12. 发明申请

US20120185672A1 LOCAL-ONLY SYNCHRONIZING OPERATIONS 审中-公开
标题翻译：本地同步操作
公开(公告)号：US20120185672A1
公开(公告)日：2012-07-19
申请号：US13008498
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/526 , G06F12/0815 , G06F2209/521
摘要： Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The second memory layer is shared via coherency operations among the first core and one or more second cores. The first core may perform one or more synchronization operations on the shared data without requiring interaction from the second memory layer.
摘要翻译：通过核心对由多个核心共享的数据执行一系列连续同步操作可以包括指示即将到来的对共享数据的同步操作的第一核心。第二存储器层存储共享数据并跟踪第一核心对共享数据的所有权。通过第一核心和一个或多个第二核心之间的一致性操作来共享第二存储器层。第一核可以对共享数据执行一个或多个同步操作，而不需要来自第二存储器层的交互。

13. 发明授权

US08117288B2 Optimizing layout of an application on a massively parallel supercomputer 失效
标题翻译：在大型并行超级计算机上优化应用程序的布局
公开(公告)号：US08117288B2
公开(公告)日：2012-02-14
申请号：US10963101
申请日：2004-10-12
申请人： Gyan V. Bhanot , Alan Gara , Philip Heidelberger , Eoin M. Lawless , James C. Sexton , Robert E. Walkup
发明人： Gyan V. Bhanot , Alan Gara , Philip Heidelberger , Eoin M. Lawless , James C. Sexton , Robert E. Walkup
IPC分类号： G06F15/177
CPC分类号： G06F9/5066
摘要： A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σi,jC(i,j)H(i,j)− where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.
摘要翻译：描述了在大型并行超级计算机上优化问题布局的通用计算机实现方法和装置。该方法采用数组形式的任意问题的通信矩阵作为输入，其条目C（i，j）是从域i到域j传送的数据量。给定C（i，j），首先实现启发式映射，其尝试顺序地将域及其通信邻居映射到超级计算机节点或超级计算机环面上的近邻节点，同时保持域的数量映射到超级计算机节点常数（尽可能多）。接下来，使用具有自由能的蒙特卡罗模拟（成本函数）F =＆Sgr; i，jC（i，j）H（i，j），从初始映射生成马尔科夫链映射。其中H（i，j）域i和域j之间的超级计算机环面上的最小跳数。在测试的情况下，发现该方法产生良好的映射，并且有可能被用作并行代码的通用布局优化工具。此时，实现测试方法的序列号未优化，以便在典型的PC上找到最佳映射的计算时间可以为几个小时。对于生产实现，将需要我们的算法的良好的并行代码，这本身可以在超级计算机上实现。

14. 发明申请

US20110173488A1 NON-VOLATILE MEMORY FOR CHECKPOINT STORAGE 失效
标题翻译：用于检查点存储的非易失性存储器
公开(公告)号：US20110173488A1
公开(公告)日：2011-07-14
申请号：US13004005
申请日：2011-01-10
申请人： Matthias A. Blumrich , Dong Chen , Thomas M. Cipolla , Paul W. Coteus , Alan Gara , Philip Heidelberger , Mark J. Jeanson , Gerard V. Kopcsay , Martin Ohmacht , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , Thomas M. Cipolla , Paul W. Coteus , Alan Gara , Philip Heidelberger , Mark J. Jeanson , Gerard V. Kopcsay , Martin Ohmacht , Todd E. Takken
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/1438 , G06F2201/82 , G06F2201/84
摘要： A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.
摘要翻译：一种用于在高性能并行计算系统中支持系统发起的检查点并将检查点数据存储到非易失性存储器存储设备的系统，方法和计算机程序产品。系统和方法产生选择性控制信号，以在存在与在节点处运行的用户应用相关联的消息传送活动的情况下执行系统相关数据的检查点。检查点由系统启动，使得即使在存在包括正在进行的用户消息活动的高度并行计算机上的用户应用的情况下，也可以获得多个网络节点的检查点数据。在一个实施例中，非易失性存储器是可插拔闪存卡。

15. 发明申请

US20110172984A1 EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION 失效
标题翻译：静态芯片在带有变化的系统中的关闭效率
公开(公告)号：US20110172984A1
公开(公告)日：2011-07-14
申请号：US12727984
申请日：2010-03-19
申请人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
发明人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
IPC分类号： G06F9/455
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3237 , G06F11/24 , Y02D10/128 , Y02D10/16
摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.
摘要翻译：一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

16. 发明申请

US20110119521A1 REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统中的可重复性
公开(公告)号：US20110119521A1
公开(公告)日：2011-05-19
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

17. 发明申请

US20110047358A1 In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication 审中-公开
标题翻译：浮点异常和基于存储的异常指示的数据间路径跟踪
公开(公告)号：US20110047358A1
公开(公告)日：2011-02-24
申请号：US12543614
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/3013 , G06F9/3842 , G06F9/3865
摘要： Mechanisms are provided for tracking exceptions in the execution of vectorized code. A speculative instruction is executed on a vector element of a vector. An exception condition is detected in association with the vector element based on a result of executing the speculative instruction on the vector element. A special exception value is stored in the vector element in a vector register corresponding to the vector, indicative of the exception condition, without invoking an exception handler for the exception condition. The special exception value is propagated with the vector element of the vector through a processor architecture of the processor, without invoking the exception handler for the exception condition. An exception corresponding to the exception condition indicated by the special exception value is generated only in response to a non-speculative instruction being executed that performs a non-speculative operation on the vector element.
摘要翻译：提供了用于跟踪执行向量化代码中的异常的机制。对向量的向量元素执行推测指令。基于向量元素执行推测指令的结果，与向量元素相关联地检测异常条件。一个特殊的异常值被存储在矢量寄存器的向量寄存器中，该向量寄存器对应于向量，表示异常条件，而不调用异常条件的异常处理程序。特殊异常值通过处理器的处理器架构与向量的向量元素传播，而不调用异常条件的异常处理程序。由特殊异常值指示的异常条件对应的异常仅在响应于执行对向量元素执行非推测性操作的非推测性指令时产生。

18. 发明申请

US20070192540A1 Architectural support for thread level speculative execution 有权
标题翻译：线程级推测执行的架构支持
公开(公告)号：US20070192540A1
公开(公告)日：2007-08-16
申请号：US11351829
申请日：2006-02-10
申请人： Alan Gara , Valentina Salapura
发明人： Alan Gara , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F9/3828 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3885 , G06F9/528 , G06F12/0813 , G06F12/0897
摘要： A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread speculative execution by adding a new cache level for storing speculative values and a dedicated bus for forwarding speculative values and control. The cache level is hierarchically positioned between the cache levels L1 and L2 cache levels.
摘要翻译：用于硬件支持现有处理器核心的线程级别推测的方法和装置，而不必改变现有的处理器核心，处理器核心的接口或L1，L2或L3级别上的现有高速缓存。架构通过添加用于存储推测值的新缓存级别和用于转发推测值和控制的专用总线来支持线程推测执行。高速缓存级别被分层地定位在高速缓存级别L1和L2高速缓存级别之间。

19. 发明申请

US20060101104A1 Optimizing layout of an application on a massively parallel supercomputer 失效
标题翻译：在大型并行超级计算机上优化应用程序的布局
公开(公告)号：US20060101104A1
公开(公告)日：2006-05-11
申请号：US10963101
申请日：2004-10-12
申请人： Gyan Bhanot , Alan Gara , Philip Heidelberger , Eoin Lawless , James Sexton , Robert Walkup
发明人： Gyan Bhanot , Alan Gara , Philip Heidelberger , Eoin Lawless , James Sexton , Robert Walkup
IPC分类号： G06F1/16
CPC分类号： G06F9/5066
摘要： A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σi,jC(i,j)H(i,j)—where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.
摘要翻译：描述了在大型并行超级计算机上优化问题布局的通用计算机实现方法和装置。该方法采用数组形式的任意问题的通信矩阵作为输入，其条目C（i，j）是从域i到域j传送的数据量。给定C（i，j），首先实现启发式映射，其尝试顺序地将域及其通信邻居映射到超级计算机节点或超级计算机环面上的近邻节点，同时保持域的数量映射到超级计算机节点常数（尽可能多）。接下来，使用具有自由能量（成本函数）的蒙特卡罗模拟，从初始映射生成马尔可夫链映射，其中F =Σi，j C（i，j）H（i，j） H（i，j）是域i和域j之间的超级计算机环面上的最小跳数。在测试的情况下，发现该方法产生良好的映射，并且有可能被用作并行代码的通用布局优化工具。此时，实现测试方法的序列号未优化，以便在典型的PC上找到最佳映射的计算时间可以为几个小时。对于生产实现，将需要我们的算法的良好的并行代码，这本身可以在超级计算机上实现。

20. 发明授权

US08626957B2 Collective network for computer structures 有权
标题翻译：计算机结构集体网络
公开(公告)号：US08626957B2
公开(公告)日：2014-01-07
申请号：US13101566
申请日：2011-05-05
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。包括通过链路互连网络节点的路由器设备，以便于在虚拟网络的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

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