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161. 发明授权

US08536959B1 Substrate with built-in electronic component 有权
标题翻译：基板内置电子元器件
公开(公告)号：US08536959B1
公开(公告)日：2013-09-17
申请号：US13589531
申请日：2012-08-20
申请人： Eiji Mugiya , Tetsuo Saji , Takashi Matsuda , Hiroshi Nakamura
发明人： Eiji Mugiya , Tetsuo Saji , Takashi Matsuda , Hiroshi Nakamura
IPC分类号： H03H9/00 , H01L41/00
CPC分类号： H03H9/6483 , H03H9/02897 , H03H9/0538 , H03H9/1085 , H05K1/0271 , H05K1/056 , H05K1/185 , H05K3/4644
摘要： Provided is a substrate with a built-in electronic component that can minimize occurrence of functional anomaly, damage, or the like in a filter function section of an elastic wave filter that is caused by a deformation of a hollow cover of the elastic wave filter that is built into the substrate. The substrate with a built-in electronic component includes: an SAW filter built into a substrate, a filter function section of the SAW filter being covered by a hollow cover; and a stress absorbing layer that faces the hollow cover of the SAW filter through an insulating layer in the substrate.
摘要翻译：本发明提供一种具有内置电子部件的基板，其能够使由弹性波滤波器的中空盖的变形引起的弹性波滤波器的滤波器功能部中的功能异常，损伤等的发生最小化，内置于基材中。具有内置电子部件的基板包括：内置于基板的SAW滤波器，SAW滤波器的滤波器功能部分被中空盖覆盖; 以及通过基板中的绝缘层面向SAW滤波器的中空盖的应力吸收层。

162. 发明授权

US08485444B2 Apparatus and method for reading symbol information 有权
标题翻译：读取符号信息的装置和方法
公开(公告)号：US08485444B2
公开(公告)日：2013-07-16
申请号：US13018814
申请日：2011-02-01
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G06K7/10
CPC分类号： G06K7/14
摘要： An apparatus and method for reading symbol information enabling improvement of decoding accuracy, not being affected by the condition of a reflection coefficient waveform of a reflected light beam and the kind of symbol information to be read. The method includes: reading a reflected light beam from symbol information irradiated with a light beam; detecting peak values in a reflection coefficient waveform of the reflected light beam; calculating a first peak value according to a peak value at a high reflection coefficient side (white level) among the peak values detected; calculating a second peak value according to a peak value at a low reflection coefficient side (black level) among the peak values detected; and calculating a binarization threshold based on the first peak value and the second peak value.
摘要翻译：一种用于读取能够改善解码精度的装置和方法，不受反射光束的反射系数波形的条件和要读取的符号信息的种类的影响。该方法包括：从用光束照射的符号信息读取反射光束; 检测反射光束的反射系数波形中的峰值; 根据所检测的峰值中的高反射系数侧（白电平）的峰值计算第一峰值; 根据所检测的峰值中的低反射系数侧（黑电平）的峰值计算第二峰值; 以及基于所述第一峰值和所述第二峰值计算二值化阈值。

163. 发明申请

US20130033275A1 FUEL PROPERTY DETECTION DEVICE 审中-公开
标题翻译：燃油特性检测装置
公开(公告)号：US20130033275A1
公开(公告)日：2013-02-07
申请号：US13483206
申请日：2012-05-30
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01N33/2852 , G01N27/226
摘要： A first electrode has a fuel passage. A second electrode defines a predetermined gap with the first electrode in the fuel passage. A third electrode defines a predetermined gap with the second electrode in the fuel passage. The first electrode and the second electrode form a first capacitance therebetween. The second electrode and the third electrode form a second capacitance therebetween. A circuit portion is configured to compute a property of fuel in the fuel passage according to the first capacitance and the second capacitance.
摘要翻译：第一电极具有燃料通道。第二电极在燃料通道中与第一电极限定预定的间隙。第三电极在燃料通道中与第二电极限定预定的间隙。第一电极和第二电极在它们之间形成第一电容。第二电极和第三电极之间形成第二电容。电路部分被配置为根据第一电容和第二电容来计算燃料通道中的燃料的特性。

164. 发明授权

US08335125B2 Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same 有权
标题翻译：具有包括电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其控制方法
公开(公告)号：US08335125B2
公开(公告)日：2012-12-18
申请号：US13285099
申请日：2011-10-31
申请人： Takeshi Nakano , Hiroshi Nakamura , Koji Hosono
发明人： Takeshi Nakano , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C8/00
CPC分类号： G11C16/08
摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
摘要翻译：半导体存储器件包括转移电路和控制电路。该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到其源极施加第二电压，并且其漏极连接到负载。控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

165. 发明申请

US20120314497A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD 有权
标题翻译：具有高操作可靠性和高效率的芯片实现的半导体存储器件
公开(公告)号：US20120314497A1
公开(公告)日：2012-12-13
申请号：US13589523
申请日：2012-08-20
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有存储单元的第二存储单元单元构成，并且存储单元阵列通过在其两端部排列第一块而构成，在其他部分的第二块。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

166. 发明授权

US08257601B2 Substrate processing method, system and program 有权
标题翻译：基板加工方法，系统和程序
公开(公告)号：US08257601B2
公开(公告)日：2012-09-04
申请号：US13073618
申请日：2011-03-28
申请人： Seiichi Kaise , Noriyuki Iwabuchi , Shigeaki Kato , Hiroshi Nakamura , Takeshi Yokouchi , Mariko Shibata , Akira Obi
发明人： Seiichi Kaise , Noriyuki Iwabuchi , Shigeaki Kato , Hiroshi Nakamura , Takeshi Yokouchi , Mariko Shibata , Akira Obi
IPC分类号： C23F1/00
CPC分类号： H01L21/67748 , H01J37/32743 , H01L21/67201 , H01L21/6831
摘要： A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.
摘要翻译：基板处理方法用于具有基板处理装置和基板转印装置的基板处理系统。基板处理方法包括将基板转印的基板转印步骤和对基板执行预定处理的基板处理步骤。基板转印步骤和基板处理步骤包括多个操作，并且同时执行多个操作中的至少两个操作。优选地，基板处理装置包括容纳室，放置在容纳室中以安装在基板上的安装台，以及用于将传热气体供应到安装在安装台上的基板之间的空间的传热气体供应管线和安装台。

167. 发明授权

US08248849B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US08248849B2
公开(公告)日：2012-08-21
申请号：US12855481
申请日：2010-08-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

168. 发明授权

US08172949B2 Substrate processing apparatus, program for performing operation and control method thereof, and computer readable storage medium storing the program 有权
标题翻译：衬底处理装置，用于执行其操作和控制方法的程序以及存储程序的计算机可读存储介质
公开(公告)号：US08172949B2
公开(公告)日：2012-05-08
申请号：US12718699
申请日：2010-03-05
申请人： Tomoyuki Kudo , Jun Ozawa , Hiroshi Nakamura , Kazunori Kazama , Tsuyoshi Moriya , Hiroyuki Nakayama , Hiroshi Nagaike
发明人： Tomoyuki Kudo , Jun Ozawa , Hiroshi Nakamura , Kazunori Kazama , Tsuyoshi Moriya , Hiroyuki Nakayama , Hiroshi Nagaike
IPC分类号： C23C16/00 , C23F1/00 , B65G21/677 , H01L21/306
CPC分类号： H01L21/67201 , H01L21/67017 , H01L21/67253 , H01L21/67748 , Y10S414/135 , Y10S414/139
摘要： A computer readable storage medium storing a program for performing an operation method of a substrate processing apparatus is provided. The operation method includes the steps of introducing a nonreactive gas into the vacuum preparation chamber before the gate valve is opened while the substrate is transferred between the vacuum preparation chamber of the vacuum processing unit and the transfer unit, stopping introducing the nonreactive gas when an inner pressure of the vacuum preparation chamber becomes same as an atmospheric pressure, starting an evacuation process of the corrosive gas in the vacuum preparation chamber and then opening to atmosphere performed by letting the vacuum preparation chamber communicate with an atmosphere, and opening the gate valve after the step of opening to atmosphere.
摘要翻译：提供一种存储用于执行基板处理装置的操作方法的程序的计算机可读存储介质。操作方法包括以下步骤：在基板在真空处理单元的真空处理室和转印单元的真空准备室之间转移时，在闸阀打开之前将非反应性气体引入真空准备室中，当内部真空制备室的压力与大气压力相同，开始真空制备室中的腐蚀性气体的抽空处理，然后通过使真空制备室与大气连通而进入大气，并在该真空制备室之后打开闸阀向大气开放的一步。

169. 发明申请

US20120099694A1 FAST REACTOR 有权
标题翻译：快速反应器
公开(公告)号：US20120099694A1
公开(公告)日：2012-04-26
申请号：US13266489
申请日：2010-04-27
申请人： Takanari Inatomi , Ayano Ebihara , Hiroshi Nakamura , Hideo Kobayashi , Katsushi Hasegawa
发明人： Takanari Inatomi , Ayano Ebihara , Hiroshi Nakamura , Hideo Kobayashi , Katsushi Hasegawa
IPC分类号： G21C11/00 , G21C15/02
CPC分类号： G21C1/322 , G21C1/02 , G21C11/022 , G21C15/02 , G21C15/247 , Y02E30/34
摘要： A fast reactor 1 includes: a reactor vessel 7 accommodating therein a core 2 and a primary coolant 21; a core support 13 supporting the core 2 from below; and a bulkhead 6 disposed on the core support 13, the bulkhead 6 extending upward and surrounding the core 2 from a lateral side. Between an inner surface of the reactor vessel 7 and the bulkhead 6, there is disposed an intermediate heat exchanger 15 configured to cool the primary coolant 21, and an electromagnetic pump 14 configured to pressurize the cooled primary coolant 21. A neutron shield 8 supported by an upper supporting plate 29 from above is disposed below the electromagnetic pump 14. The upper supporting plate 29 has an opening 29a. Between an outlet 14b of the electromagnetic pump 14 and the upper supporting plate 29, there is disposed a coolant guide mechanism 17 configured to guide the pressurized primary coolant 21 from the electromagnetic pump 14 to the neutron shield through the opening 29a of the upper supporting plate 29.
摘要翻译：快堆1包括：反应容器7，容纳有芯2和主冷却剂21; 核心支撑13支撑下面的核心2; 以及设置在芯支撑件13上的隔板6，隔板6从外侧向上延伸并围绕芯2。在反应堆容器7的内表面和隔板6之间设置有构造成冷却主冷却剂21的中间热交换器15和构造成对冷却的一次冷却剂21加压的电磁泵14.中子屏蔽8由来自上方的上支撑板29设置在电磁泵14的下方。上支撑板29具有开口29a。在电磁泵14的出口14b和上支撑板29之间设置有冷却剂引导机构17，其构造成通过上支撑板的开口29a将加压的一次冷却剂21从电磁泵14引导到中子屏蔽 29。

170. 发明申请

US20120092759A1 SOLAR CONTROL GLASS AND SOLAR CONTROL DOUBLE GLASS 有权
标题翻译：太阳能控制玻璃和太阳能控制双层玻璃
公开(公告)号：US20120092759A1
公开(公告)日：2012-04-19
申请号：US13380780
申请日：2010-06-24
申请人： Yuji Suzuki , Hiroshi Nakamura
发明人： Yuji Suzuki , Hiroshi Nakamura
IPC分类号： G02B5/26
CPC分类号： B32B17/10018 , B32B17/10 , B32B17/10055 , B32B17/10174 , B32B17/10633 , B32B17/10697 , B32B17/10788 , B32B2367/00 , C03C17/3405 , E06B3/6715 , G02B5/208
摘要： A heat-ray shielding glass products (e.g., solar control double glass) which have excellent heat-ray shielding property, especially thermal insulation property and enhanced durability under the condition of existence of moisture (under high humidity), and which can be prepared in low cost is provided. The solar control double glass 40 comprises a solar control glass 30 having a glass plate 21 and a heat-ray reflection layer 24 comprising an electrically-conductive polymer provided thereon and another glass plate 37, the solar control glass and the another glass being arranged at an interval such that the heat-ray reflection layer faces the another glass and the interval forming a hollow layer 38, and the heat-ray reflection layer 24 has a surface resistivity of not more than 10,000Ω/□.
摘要翻译：具有优异的热射线屏蔽性，特别是保温性和在潮湿（高湿度）的条件下提高的耐久性）的热射线屏蔽玻璃制品（例如太阳能控制双层玻璃），其可以制备在提供低成本。太阳能控制双层玻璃40包括具有玻璃板21的太阳能控制玻璃30和设置在其上的导电聚合物的热射线反射层24，另一玻璃板37，太阳能控制玻璃和另一玻璃布置在使得热射线反射层面对另一玻璃的间隔和形成中空层38的间隔，并且热射线反射层24的表面电阻率不大于10,000＆OHgr /□。

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