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131. 发明授权

US08928385B2 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same 有权
标题翻译：控制片上系统的时钟的方法，包括功能块，芯片上的系统和包括其的半导体系统
公开(公告)号：US08928385B2
公开(公告)日：2015-01-06
申请号：US13687637
申请日：2012-11-28
申请人： Dong Keun Kim , Sun Cheol Kwon , Si Young Kim , Jae Gon Lee , Jung Hun Heo
发明人： Dong Keun Kim , Sun Cheol Kwon , Si Young Kim , Jae Gon Lee , Jung Hun Heo
IPC分类号： H03K3/00 , H03K21/00 , G06F1/32 , G06F1/08 , H03K19/00 , H03K21/10
CPC分类号： H03K5/04 , G06F1/08 , G06F1/324 , H03K19/0016 , H03K21/00 , H03K21/10 , Y02D10/126 , Y02D50/20
摘要： A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
摘要翻译：片上系统包括时钟控制器，其被配置为基于至少一个功能块的操作状态从活动状态到空闲状态的改变来减小至少一个功能块的操作频率。在包括至少一个功能块的操作片上系统的方法中，至少一个功能块的工作频率基于至少一个功能块从激活状态的操作状态的改变而减小到空闲状态。工作频率降低大于零。

132. 发明授权

US08917122B1 Frequency dividers 有权
标题翻译：分频器
公开(公告)号：US08917122B1
公开(公告)日：2014-12-23
申请号：US14019875
申请日：2013-09-06
申请人： Infineon Technologies AG
发明人： Heiko Koerner
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K21/02
CPC分类号： H03K21/026 , H03K21/10
摘要： Various embodiments relate to frequency dividers. A current of a current source of the frequency divider is controlled based on a property of an output signal of the frequency divider.
摘要翻译：各种实施例涉及分频器。基于分频器的输出信号的特性来控制分频器的电流源的电流。

133. 发明授权

US08867696B2 Fractional frequency divider 有权
标题翻译：分数分频器
公开(公告)号：US08867696B2
公开(公告)日：2014-10-21
申请号：US13172491
申请日：2011-06-29
申请人： Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
发明人： Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
IPC分类号： H03K21/00 , H03K5/156 , H03K21/10 , H03K23/66 , H03K23/68
CPC分类号： H03K5/156 , H03K21/10 , H03K23/662 , H03K23/68
摘要： A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.
摘要翻译：一种分数分频器，包括用于产生具有针对原始定时信号的每k个脉冲具有j个脉冲的降频定时信号的分频单元，其中j和k各自是整数; 以及相位校正电路，其适于选择性地将所述降频定时信号的第j个脉冲移位第一固定时间段。

134. 发明申请

US20140117202A1 DRIVER CIRCUIT AND READOUT CIRCUIT 有权
标题翻译：驱动电路和读出电路
公开(公告)号：US20140117202A1
公开(公告)日：2014-05-01
申请号：US13894526
申请日：2013-05-15
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-kun YOON , Young KIM , Chae-hun LEE , Chang-jung KIM , Jae-chul PARK
IPC分类号： H03K21/10 , G01J1/44
CPC分类号： H03K21/10 , G01J1/44 , G01T1/247
摘要： A driver circuit outputs a result of classifying and counting photons based on one or more energy levels to a column line. The driver circuit includes a multiplexer for receiving the result from a counter, a driving inverter for receiving a signal from the multiplexer and a power supply, and a switch connected between the power supply and an input terminal of the driving inverter.
摘要翻译：驱动器电路输出基于一个或多个能量级别的光子对列线进行分类和计数的结果。驱动器电路包括用于从计数器接收结果的多路复用器，用于从多路复用器接收信号的驱动逆变器和电源，以及连接在电源和驱动逆变器的输入端之间的开关。

135. 发明授权

US08565368B1 Wide range multi-modulus divider in fractional-N frequency synthesizer 有权
$Wide range multi-modulus divider in fractional-N frequency synthesizer$
标题翻译：分数N频率合成器中的宽范围多模分频器
公开(公告)号：US08565368B1
公开(公告)日：2013-10-22
申请号：US13481489
申请日：2012-05-25
申请人： Juinn-Yan Chen , San-Chieh Chou
发明人： Juinn-Yan Chen , San-Chieh Chou
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K21/10 , H03K23/68
摘要： A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.
摘要翻译：多模式分配器包括级联的n个双模均衡器单元的链，并以波纹配置连接，其中分配器单元的最后（n-k）是状态驻留双模除法器单元。当分频器电池旁路时，状态驻留双模除法器单元被强制为给定的逻辑状态。状态驻留双模式分频器电池确保多模式分频器可在不同数量的单元之间切换，无需时钟毛刺或时钟错误。因此，多模式分频器能够实现宽分割范围，并且在分频比之间无缝转换。

136. 发明申请

US20130271188A1 COMPACT HIGH FREQUENCY DIVIDER 有权
标题翻译：紧凑型高频分频器
公开(公告)号：US20130271188A1
公开(公告)日：2013-10-17
申请号：US13445075
申请日：2012-04-12
申请人： Ngar Loong A. Chan
发明人： Ngar Loong A. Chan
IPC分类号： H03B19/14
CPC分类号： H03B19/14 , H03K3/35613 , H03K21/026 , H03K21/10
摘要： A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS and NMOS transistors, in which the input signal to be frequency divided is supplied to the body of the PMOS and/or NMOS transistors. The input signal may be coupled to the PMOS and/or NMOS transistors through capacitive or inductive coupling. The input signal to the PMOS and/or NMOS transistors may be generated by a voltage controlled oscillator circuit. With the frequency divider circuit having inputs signals coupled to the body of the PMOS and/or NMOS transistors supply voltages as low as 0.5 Volts may be possible.
摘要翻译：具有两级晶体管的分频器电路在低电源电压下具有改进的性能。电路可以包括交叉耦合的PMOS和NMOS晶体管，其中待分频的输入信号被提供给PMOS和/或NMOS晶体管的主体。输入信号可以通过电容或电感耦合耦合到PMOS和/或NMOS晶体管。可以通过压控振荡器电路产生到PMOS和/或NMOS晶体管的输入信号。利用具有耦合到PMOS和/或NMOS晶体管的输入信号的分频器电路，可以提供低至0.5伏特的电压。

137. 发明授权

US08558575B1 Clock generation for N.5 modulus divider 有权
标题翻译： N.5模数分频器的时钟生成
公开(公告)号：US08558575B1
公开(公告)日：2013-10-15
申请号：US13427955
申请日：2012-03-23
申请人： Brian Abernethy
发明人： Brian Abernethy
IPC分类号： H03K19/21
CPC分类号： H03K21/10 , H03K19/21 , H03K23/68 , H03L7/1803 , H03L7/1972 , H03L7/1974
摘要： A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.
摘要翻译：提供一种用于产生用于N.5模数分频的输出时钟的系统。边缘滑移电路接受模数计数，除数选择信号和具有大于模数计数频率的频率的时钟信号。边缘滑移电路还具有接收输出时钟信号的输入端和用于提供时钟滑差信号（NE）的输出。异或（XOR）具有接受缓冲时钟信号（NF）和时钟转移信号（NE）的输入。 XOR具有输出以提供输出时钟信号。当时钟滑移信号不改变逻辑电平时，输出时钟信号的频率等于缓冲的时钟信号频率，没有跳过的时钟沿。或者，当时钟滑移信号改变逻辑电平时，输出时钟信号频率等于具有跳过时钟边沿的缓冲时钟信号频率。

138. 发明授权

US08502573B2 Frequency divider for generating output clock signal with duty cycle different from duty cycle of input clock signal 有权
标题翻译：用于产生输出时钟信号的分频器，占空比不同于输入时钟信号的占空比
公开(公告)号：US08502573B2
公开(公告)日：2013-08-06
申请号：US13658809
申请日：2012-10-23
申请人： Mediatek Inc.
发明人： Ming-Da Tsai
IPC分类号： H03K21/00
CPC分类号： H03K23/425 , G06F1/08 , H03K3/356173 , H03K21/023 , H03K21/10
摘要： A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.
摘要翻译：分频器包括多个逻辑电路块。每个逻辑电路块具有多个控制端子。一个逻辑电路块的控制端中的至少一个被布置成接收具有第一占空比的输入时钟信号。逻辑电路块中的一个的剩余控制端中的至少一个被布置成通过正反馈耦合另一个逻辑电路块。所述剩余控制端中的至少一个的时钟信号具有与第一占空比不同的第二占空比。每个逻辑电路块包括并联在第一参考电压和输出端之间的多个第一晶体管，以及串联耦合在第二参考电压和输出端之间的多个第二晶体管。

139. 发明申请

US20130156147A1 HIGH SPEED COUNTER APPARATUS 审中-公开
标题翻译：高速计数器
公开(公告)号：US20130156147A1
公开(公告)日：2013-06-20
申请号：US13716006
申请日：2012-12-14
申请人： Electronics and Telecommunications Research Institute
发明人： Kunal Jayant Dadia
IPC分类号： H03K21/02
CPC分类号： H03K21/026 , H03K21/10
摘要： Disclosed is a high speed counter apparatus. The high speed counter apparatus includes a first counter configured to perform a count on the lower bits of the final output signal in response to a first clock signal, a second counter configured to perform a count on the upper bits of the final output signal in response to a second clock signal, and a clock signal generator configured to generate the second clock signal from the first clock signal. In accordance with the present invention, power consumption and a bottleneck phenomenon in an upper bit counter can be reduced because a second clock signal for operating the upper bit counter is synchronized with a first clock signal for operating the lower bit counter at a frequency lower than that of the clock signal for operating the lower bit counter.
摘要翻译：公开了一种高速计数器装置。高速计数器装置包括：第一计数器，被配置为响应于第一时钟信号对最终输出信号的低位执行计数;第二计数器，被配置为响应于对最终输出信号的高位进行计数以及被配置为从第一时钟信号产生第二时钟信号的时钟信号发生器。根据本发明，由于用于操作高位计数器的第二时钟信号与第一时钟信号同步，所以可以降低高位计数器中的功耗和瓶颈现象，以便以低于用于操作低位计数器的时钟信号。

140. 发明申请

US20130021070A1 LOW-POWER FREQUENCY DIVIDERS 有权
标题翻译：低功率频率分频器
公开(公告)号：US20130021070A1
公开(公告)日：2013-01-24
申请号：US13625642
申请日：2012-09-24
申请人： Analog Devices, Inc.
发明人： Hyman Shanan
IPC分类号： H03K21/00
CPC分类号： H03B19/00 , H03K3/356191 , H03K21/023 , H03K21/10
摘要： A bias-shaping circuit for adjusting power consumption in a frequency divider to a temperature-dependent minimum includes a temperature-dependent bias source for producing a temperature-dependent bias. The bias is combined with an input signal to create an output bias. The output bias changes in response to a change in temperature to compensate for at least a portion of a temperature-induced change in the frequency divider, thereby adjusting power consumption in the frequency divider to a temperature-dependent minimum.
摘要翻译：用于将分频器中的功率消耗调节至温度依赖最小值的偏置整形电路包括用于产生温度依赖偏置的温度依赖偏置源。偏置与输入信号组合以产生输出偏置。输出偏置响应于温度变化而变化以补偿分频器中温度引起的变化的至少一部分，从而将分频器中的功率消耗调节到依赖于温度的最小值。

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