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1. 发明授权

US08565368B1 Wide range multi-modulus divider in fractional-N frequency synthesizer 有权
$Wide range multi-modulus divider in fractional-N frequency synthesizer$
标题翻译：分数N频率合成器中的宽范围多模分频器
公开(公告)号：US08565368B1
公开(公告)日：2013-10-22
申请号：US13481489
申请日：2012-05-25
申请人： Juinn-Yan Chen , San-Chieh Chou
发明人： Juinn-Yan Chen , San-Chieh Chou
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K21/10 , H03K23/68
摘要： A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.
摘要翻译：多模式分配器包括级联的n个双模均衡器单元的链，并以波纹配置连接，其中分配器单元的最后（n-k）是状态驻留双模除法器单元。当分频器电池旁路时，状态驻留双模除法器单元被强制为给定的逻辑状态。状态驻留双模式分频器电池确保多模式分频器可在不同数量的单元之间切换，无需时钟毛刺或时钟错误。因此，多模式分频器能够实现宽分割范围，并且在分频比之间无缝转换。

2. 发明授权

US07009540B1 Method for designing a noise shaper with a single loop distributed feedback delta-sigma modulator 有权
标题翻译：用单环路分布式反馈Δ-Σ调制器设计噪声整形器的方法
公开(公告)号：US07009540B1
公开(公告)日：2006-03-07
申请号：US10905425
申请日：2005-01-04
申请人： Juinn-Yan Chen , Wei-Gian Chen , Zuoqin Wang
发明人： Juinn-Yan Chen , Wei-Gian Chen , Zuoqin Wang
IPC分类号： H03M3/00
CPC分类号： G06F17/5063
摘要： A method for designing a noise shaper with a single loop distributed feedback delta-sigma modulator includes following steps: (a) determining a delta-sigma modulator comprising a plurality of parameters according to an order of the noise shaper; (b) deriving a noise transfer function comprising a plurality of coefficients corresponding to the parameters of the delta-sigma modulator according to the delta-sigma modulator; (c) determining a high-pass filter corresponding to the delta-sigma modulator according to a default requirement; (d) solving the coefficients of the noise transfer function according to the high-pass filter; and (e) feeding the solved coefficients in step (d) into the parameters of the delta-sigma modulator for completing the noise shaper.
摘要翻译：用于设计具有单环分布式反馈Δ-Σ调制器的噪声整形器的方法包括以下步骤：（a）根据噪声整形器的顺序确定包括多个参数的Δ-Σ调制器; （b）导出噪声传递函数，所述噪声传递函数包括与所述Δ-Σ调制器的所述Δ-Σ调制器的参数对应的多个系数; （c）根据默认要求确定对应于Δ-Σ调制器的高通滤波器; （d）根据高通滤波器求解噪声传递函数的系数; 和（e）将步骤（d）中的求解的系数馈送到用于完成噪声整形器的Δ-Σ调制器的参数。

3. 发明授权

US06803834B1 Sigma-delta modulated discrete time oscillator 有权
标题翻译： Sigma-delta调制离散时间振荡器
公开(公告)号：US06803834B1
公开(公告)日：2004-10-12
申请号：US10442921
申请日：2003-05-22
申请人： Juinn-Yan Chen
发明人： Juinn-Yan Chen
IPC分类号： H03B2800
CPC分类号： H03L7/0994
摘要： A sigma-delta modulated discrete time oscillator. The sigma-delta modulated discrete time oscillator comprises a synchronous counter and a sigma-delta modulator. The sigma-delta modulator operating in a first clock receives a control signal to generate a divider pattern output. The control signal provides a DC value for the frequency of the first clock. The divider pattern comprises a plurality of numbers, values of which are synchronous with the rate of the first clock. The synchronous counter operates in a second clock. In the synchronous counter, the second clock is divided by the divider pattern to generate the first clock. The frequency of the second clock is much higher than the frequency of the first clock.
摘要翻译： Σ-Δ调制离散时间振荡器。 Σ-Δ调制离散时间振荡器包括同步计数器和Σ-Δ调制器。在第一时钟中工作的Σ-Δ调制器接收控制信号以产生分频器模式输出。控制信号为第一时钟的频率提供DC值。分频器模式包括多个数字，其值与第一时钟的速率同步。同步计数器工作在第二个时钟。在同步计数器中，第二个时钟由分频器模式除以产生第一个时钟。第二个时钟的频率远高于第一个时钟的频率。

4. 发明授权

US06304844B1 Spelling speech recognition apparatus and method for communications 失效
标题翻译：拼写语音识别装置和通信方法
公开(公告)号：US06304844B1
公开(公告)日：2001-10-16
申请号：US09538657
申请日：2000-03-30
申请人： James Pan , Yoon Kim , Josephine Chang , Juinn-Yan Chen
发明人： James Pan , Yoon Kim , Josephine Chang , Juinn-Yan Chen
IPC分类号： G10L1502
CPC分类号： G10L15/187 , G10L15/02 , G10L2015/086
摘要： An accurate speech recognition system capable of rapidly processing greater varieties of words and operable in many different devices, but without the computational power and memory requirements, high power consumption, complex operating system, high costs, and weight of traditional systems. The utilization of individual letter utterances to transmit words allows voice information transfer for both person-to-person and person-to-machine communication for mobile phones, PDAs, and other communication devices. This invention is an apparatus and method for a speech recognition system comprising a microphone, front-end signal processor for generating parametric representations of speech input signals, a pronunciation database, a letter similarity comparator for comparing the parametric representation of the input signals with the parametric representations of letter pronunciations, and generating a sequence of associations between the input speech and the letters in the pronunciation database, a vocabulary database, a word similarity comparator for comparing an aggregated plurality of the letters with the words in the vocabulary database and generating a sequence of associations between them, and a display for displaying the selected letters and words for confirmation.
摘要翻译：一种精确的语音识别系统，能够快速处理更多种类的词语，并可在许多不同的设备中运行，但无需计算能力和内存要求，高功耗，复杂的操作系统，高成本和传统系统的重量。使用单个字母的话语来传输话语，可以为移动电话，PDA和其他通信设备的个人对个人和个人到机器的通信进行语音信息传输。本发明是一种用于语音识别系统的装置和方法，其包括麦克风，用于产生语音输入信号的参数表示的前端信号处理器，发音数据库，字母相似性比较器，用于将输入信号的参数表示与参数字母发音的表示，以及在发音数据库中产生输入语音和字母之间的关联序列，词汇数据库，词汇相似性比较器，用于将汇总的多个字母与词汇数据库中的单词进行比较，并产生序列它们之间的关联，以及用于显示所选择的字母和单词以进行确认的显示。

5. 发明授权

US06759885B2 Self-calibrating clock generator for generating process and temperature independent clock signals 有权
公开(公告)号：US06759885B2
公开(公告)日：2004-07-06
申请号：US10064610
申请日：2002-07-30
申请人： Juinn-Yan Chen
发明人： Juinn-Yan Chen
IPC分类号： H03K300
CPC分类号： G06F1/06 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00143
摘要： A clock analyzer includes an input port for receiving a reference clock signal from an external source, a plurality of functionally identical delay cells for delaying the reference clock signal and generating a plurality of delayed clock signals, each delayed clock signal being delayed by a unique number of delay cells, and at least one comparator for comparing the reference clock signal to the plurality of delayed clock signals and choosing a selected clock signal from the plurality of delayed clock signals that at least partially overlaps the reference clock signal.

6. 发明申请

US20080208488A1 Device for Detecting Impact and Use Thereof 审中-公开
标题翻译：用于检测其影响和使用的装置
公开(公告)号：US20080208488A1
公开(公告)日：2008-08-28
申请号：US11616237
申请日：2006-12-26
申请人： Joe Shih-Horng Yang , Wen-Yen Wang , Juinn-Yan Chen
发明人： Joe Shih-Horng Yang , Wen-Yen Wang , Juinn-Yan Chen
IPC分类号： G01L5/00 , G08B3/00 , G06F11/00 , G06F15/00
CPC分类号： F41J5/052 , F41J5/056
摘要： The present invention relates to a device for detecting an impact and use thereof.
摘要翻译：本发明涉及一种用于检测冲击及其使用的装置。

7. 发明授权

US06710729B1 Idle channel tone and periodic noise suppression for sigma-delta modulator using feedback-quantizer 有权
标题翻译：使用反馈量化器对Σ-Δ调制器进行空闲通道音和周期性噪声抑制
公开(公告)号：US06710729B1
公开(公告)日：2004-03-23
申请号：US10267843
申请日：2002-10-10
申请人： Juinn-Yan Chen
发明人： Juinn-Yan Chen
IPC分类号： H03M300
CPC分类号： H03M3/334 , H03M3/33 , H03M3/43 , H03M3/454
摘要： A sigma-delta modulator. The sigma-delta modulator comprises an integrator, a first quantizer, a dither generator and an adding device. An input terminal of the first quantizer and an input terminal of the dither generator are coupled to an output terminal of the integrator. The first quantizer generates a first random signal. The dither generator comprises a second quantizer for generating a second random signal, an input terminal thereof coupling to the output of the integrator; a random sequencer for receiving the first random signal and the second random signal to produce a third random signal output; and an attenuator for attenuating the third random signal to produce a dither signal to output. The dither signal is added to an input terminal of the integrator by the adding device.
摘要翻译： Σ-Δ调制器。 Σ-Δ调制器包括积分器，第一量化器，抖动发生器和加法器件。第一量化器的输入端和抖动发生器的输入端耦合到积分器的输出端。第一量化器产生第一随机信号。抖动发生器包括用于产生第二随机信号的第二量化器，其耦合到积分器的输出的输入端; 随机定序器，用于接收第一随机信号和第二随机信号以产生第三随机信号输出; 以及用于衰减第三随机信号以产生抖动信号以输出的衰减器。抖动信号由加法装置加到积分器的输入端。

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