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131. 发明授权

US07928420B2 Phase change tip storage cell 有权
标题翻译：相变尖端存储单元
公开(公告)号：US07928420B2
公开(公告)日：2011-04-19
申请号：US10732580
申请日：2003-12-10
申请人： David V. Horak , Chung H. Lam , Hon-Sum P. Wong
发明人： David V. Horak , Chung H. Lam , Hon-Sum P. Wong
IPC分类号： H01L21/00 , H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1691
摘要： A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.
摘要翻译：具有一个或多个存储单元的存储单元，集成电路（IC）芯片，其可以是存储单元阵列，以及形成存储单元和IC的方法。每个存储单元包括触针，其尖端是相变材料。相变尖端可以夹在电极和导电材料之间，例如氮化钛（TiN），氮化钽（TaN）或n型半导体。相变层可以是硫族化物，特别是锗（Ge），锑（Sb），碲（Te）（GST）层。

132. 发明授权

US07901980B2 Self-aligned in-contact phase change memory device 有权
标题翻译：自对准接触相变存储器件
公开(公告)号：US07901980B2
公开(公告)日：2011-03-08
申请号：US12537317
申请日：2009-08-07
申请人： Roger W. Cheek , Chung H. Lam , Stephen M. Rossnagel , Alejandro G. Schrott
发明人： Roger W. Cheek , Chung H. Lam , Stephen M. Rossnagel , Alejandro G. Schrott
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L21/76831 , H01L27/2436 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode.
摘要翻译：存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层层。然后在中间绝缘层上方的绝缘层中限定通孔，产生用间隔物蚀刻的通道，在中间绝缘层中限定孔，去除中间绝缘层之上的所有绝缘层，将整个孔填充到相变材料，并在相变材料上形成上电极。另外，与上电极形成位线连接。

133. 发明申请

US20110049462A1 FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL 有权
标题翻译：平底下电极用于相变记忆体
公开(公告)号：US20110049462A1
公开(公告)日：2011-03-03
申请号：US12550048
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/768 , H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

134. 发明申请

US20110038199A1 MEASUREMENT METHOD FOR READING MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 失效
标题翻译：用于读取多级存储器单元的测量方法使用测量时间延迟作为等级定义的特性参数
公开(公告)号：US20110038199A1
公开(公告)日：2011-02-17
申请号：US12542146
申请日：2009-08-17
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/06 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value.
摘要翻译：存储器系统包括被配置为表示至少两个二进制值的存储器单元，耦合到存储单元的位线，以及耦合到位线的第一和第二比较器，其分别将第一和第二参考值与位线的参数。该系统还包括配置成测量位线参数衰减的时间的第一和第二定时器。该系统还包括耦合到第一和第二定时器的逻辑单元，其选择位线的参数从第一值或第二值衰减的时间。

135. 发明授权

US07879728B2 Sub-lithographic printing method 有权
标题翻译：亚平版印刷法
公开(公告)号：US07879728B2
公开(公告)日：2011-02-01
申请号：US12018316
申请日：2008-01-23
申请人： Chung H. Lam , Hemantha K. Wickramasinghe
发明人： Chung H. Lam , Hemantha K. Wickramasinghe
IPC分类号： H01L21/311
CPC分类号： H01L21/0337
摘要： A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.
摘要翻译：一种在衬底中形成次光刻沟槽结构的方法以及包括衬底中的次光刻沟槽结构的集成电路。该方法包括用光刻掩模形成一组沟槽，并且用一组间隔块填充该组沟槽，该组间隔块包含彼此分离地拆卸的两个交替间隔物材料。在一个实施例中，形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。间隔材料层的数量为n / 2，每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。

136. 发明授权

US07864566B2 Phase change memory programming method without reset over-write 有权
标题翻译：相位改变存储器编程方法，无复位重写
公开(公告)号：US07864566B2
公开(公告)日：2011-01-04
申请号：US12166934
申请日：2008-07-02
申请人： Matthew J. Breitwisch , Chung H. Lam
发明人： Matthew J. Breitwisch , Chung H. Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
摘要： A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a reset threshold voltage and greater than a set threshold voltage. The reset write current pulse writing a RESET state to the phase change memory cell. The method additionally comprised of applying a set write current pulse through the phase change memory element such that the set write current pulse produces a voltage drop across the phase change memory element that is equal to or greater than the reset threshold voltage. The set write current pulse writing a SET state to the phase change memory cell.
摘要翻译：一种编程避免RESET重写的相变存储器件的方法。所述方法部分地包括通过将所述复位写入电流脉冲施加到所述相变存储元件，使得所述复位写入电流脉冲在所述相变存储元件上产生小于复位阈值电压并大于设定阈值电压的电压降。复位写入电流脉冲将RESET状态写入相变存储单元。该方法还包括通过相变存储元件施加设置的写入电流脉冲，使得所设置的写入电流脉冲在相变存储器元件上产生等于或大于复位阈值电压的电压降。该设定的写入电流脉冲将SET状态写入相变存储单元。

137. 发明申请

US20100328994A1 PHASE CHANGE MEMORY WITH FINITE ANNULAR CONDUCTIVE PATH 有权
标题翻译：相位变化记忆与有限的环形导电路径
公开(公告)号：US20100328994A1
公开(公告)日：2010-12-30
申请号：US12491816
申请日：2009-06-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译：相变存储器件及其编程方法。该方法包括确定相变存储器件中的存储器单元的最大可能电阻。该方法包括确定相变存储器件中存储单元的高电阻状态。该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

138. 发明申请

US20100301409A1 VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US20100301409A1
公开(公告)日：2010-12-02
申请号：US12851232
申请日：2010-08-05
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

139. 发明授权

US07825460B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US07825460B2
公开(公告)日：2010-11-02
申请号：US11516208
申请日：2006-09-06
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在前述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

140. 发明申请

US20100226161A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 有权
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20100226161A1
公开(公告)日：2010-09-09
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

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