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1. 发明授权

US08383501B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US08383501B2
公开(公告)日：2013-02-26
申请号：US13185055
申请日：2011-07-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

2. 发明授权

US08378328B2 Phase change memory random access device using single-element phase change material 失效
标题翻译：相变存储器随机存取装置采用单元相变材料
公开(公告)号：US08378328B2
公开(公告)日：2013-02-19
申请号：US12036215
申请日：2008-02-22
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2436 , H01L45/1226 , H01L45/14
摘要： A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).
摘要翻译：具有单个元件相变薄膜层的相变存储单元; 以及耦合到单个元件相变薄膜层的第一电极和第二电极。 A电流从第一电极流向单一元件相变薄膜层，并通过第二电极。单元相变薄膜层包括单一元素相变材料。单相相变薄膜层可以小于5纳米厚。单元相变材料的结晶温度可以通过其厚度来控制。在一个实施例中，单个元件相变薄膜层被配置为在室温（25摄氏度）下是无定形的。在一个实施例中，单元相变薄膜层由锑（Sb）组成。

3. 发明申请

US20130001500A1 PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR 有权
公开(公告)号：US20130001500A1
公开(公告)日：2013-01-03
申请号：US13612552
申请日：2012-09-12
申请人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
发明人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

4. 发明申请

US20130001499A1 Compressive Structure for Enhancing Contact of Phase Change Material Memory Cells 审中-公开
标题翻译：用于增强相变材料记忆单元接触的压缩结构
公开(公告)号：US20130001499A1
公开(公告)日：2013-01-03
申请号：US13171210
申请日：2011-06-28
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/06 , H01L21/62
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.
摘要翻译：一种用于制造PCM器件的方法包括形成电介质，通过在该区域中形成通孔开口，在电介质的表面上的区域开始在电介质中产生通孔，并将该开口延伸到电介质中然后终止于电极包括电介质中的第一电极。我们形成与通孔的侧壁相邻的间隔层，并用PCM填充通孔。然后我们将电介质的表面去除，以在通孔的开口处留下PCM尖点，用低密度封盖膜盖住PCM尖端; 密封PCM和封盖膜以获得高密度封盖膜，其在朝向第一电极的方向上对高密度PCM施加压缩压力，以增强PCM与第一电极之间的电接触。

5. 发明授权

US08283202B2 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US08283202B2
公开(公告)日：2012-10-09
申请号：US12549997
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
发明人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成，在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。

6. 发明授权

US08278197B2 Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device 有权
标题翻译：方法可以直接在扩展垫片下方定制峰值电场的位置，以提高快速移位装置的可编程性
公开(公告)号：US08278197B2
公开(公告)日：2012-10-02
申请号：US12130460
申请日：2008-05-30
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L21/265
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
摘要翻译：本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它现有技术中的瞬时移位装置。本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。

7. 发明授权

US08110901B2 Vertical field effect transistor arrays including gate electrodes annularly surrounding semiconductor pillars 有权
标题翻译：垂直场效应晶体管阵列，包括围绕半导体柱的环形环形栅电极
公开(公告)号：US08110901B2
公开(公告)日：2012-02-07
申请号：US12851232
申请日：2010-08-05
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

8. 发明授权

US08012790B2 Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell 有权
标题翻译：化学机械抛光停止层，用于完全非晶相变记忆孔细胞
公开(公告)号：US08012790B2
公开(公告)日：2011-09-06
申请号：US12550062
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Chung H. Lam
发明人： Matthew J. Breitwisch , Chung H. Lam
IPC分类号： H01L21/06 , H01L21/108 , H01L21/44 , H01L21/20
CPC分类号： H01L21/31144 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.
摘要翻译：一种相变存储孔单元的制造方法，包括形成底电极，在所述底电极上形成第一电介质层，在所述第一电介质层上形成牺牲层，在所述牺牲层上形成隔离层，形成第二电介质层隔离层上的介电层。该方法还包括形成覆盖底部电极的通孔，延伸到牺牲层的通孔，通过牺牲层蚀刻到第一介电层，以形成限定的孔，延伸穿过牺牲层和第一介电层，沉积相变材料在牺牲层上并进入孔中，除去形成在孔外部的相变材料，去除牺牲层以暴露孔，孔垂直排列，并在孔上形成顶电极。

9. 发明授权

US07981755B2 Self aligned ring electrodes 有权
标题翻译：自对准环形电极
公开(公告)号：US07981755B2
公开(公告)日：2011-07-19
申请号：US11924073
申请日：2007-10-25
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
IPC分类号： H01L21/331 , H01L21/44
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译：本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。

10. 发明授权

US07965537B2 Phase change memory with finite annular conductive path 有权
标题翻译：具有有限环形导电路径的相变存储器
公开(公告)号：US07965537B2
公开(公告)日：2011-06-21
申请号：US12491816
申请日：2009-06-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译：相变存储器件及其编程方法。该方法包括确定相变存储器件中的存储器单元的最大可能电阻。该方法包括确定相变存储器件中存储单元的高电阻状态。该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

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