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121. 发明申请

US20090087955A1 METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS 有权
标题翻译：用于在半导体制造工艺中去除闸门上的硬掩模的方法
公开(公告)号：US20090087955A1
公开(公告)日：2009-04-02
申请号：US11864415
申请日：2007-09-28
申请人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
发明人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
IPC分类号： H01L21/3205 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/31144 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards.
摘要翻译：如下进行半导体制造工序中的门上去除硬掩模的方法。首先，在半导体衬底上形成具有硬掩模的第一栅极和第二栅极，其中第二栅极大于第一栅极。第一栅极和第二栅极可以与硅 - 锗（SiGe）源极和漏极区域相关联以形成p型晶体管。接下来，沉积光致抗蚀剂层，并且在第二栅极的硬掩模上形成光致抗蚀剂层的开口。然后，通过蚀刻完全去除第一和第二栅极上的光致抗蚀剂层。因为没有光致抗蚀剂残留物，所以第一和第二栅极上的硬掩模可以被完全去除。

122. 发明申请

US20080254588A1 METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM 审中-公开
标题翻译：用高k介质层形成晶体管的方法和形成的晶体管
公开(公告)号：US20080254588A1
公开(公告)日：2008-10-16
申请号：US11735797
申请日：2007-04-16
申请人： Harry Chuang , Kong-Beng Thei , Hung-Chih Tsai , M. Y. Wu , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Hung-Chih Tsai , M. Y. Wu , Mong-Song Liang
IPC分类号： H01L21/04
CPC分类号： H01L21/28202 , H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/78
摘要： A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %.
摘要翻译：一种用于形成半导体结构的方法包括在衬底上形成栅极电介质层。处理栅极电介质层的顶表面以至少部分地使栅极介电层氮化。经处理的栅极介电层用含氧前体进行热处理，使得至少部分氮化的栅极介电层的氮浓度在约0.5原子百分比（at。％）和约20原子％之间。

123. 发明授权

US07432179B2 Controlling gate formation by removing dummy gate structures 有权
标题翻译：通过去除虚拟栅极结构来控制栅极形成
公开(公告)号：US07432179B2
公开(公告)日：2008-10-07
申请号：US11012414
申请日：2004-12-15
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/38
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/4966 , Y10S438/917
摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.
摘要翻译：形成半导体结构的方法包括以下步骤。在有源区中的衬底上形成栅介电层。栅极电极层形成在栅极介电层上。在栅电极层上形成第一光刻胶。蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。第一个光刻胶被去除。形成覆盖栅极结构的第二光致抗蚀剂。去除不受第二光致抗蚀剂保护的虚拟图案。然后移除第二个光刻胶。

124. 发明申请

US20060188824A1 Method for improving design window 有权
标题翻译：改善设计窗口的方法
公开(公告)号：US20060188824A1
公开(公告)日：2006-08-24
申请号：US11320513
申请日：2005-12-27
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： G03F7/00
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

125. 发明授权

US08796084B2 Method for removing hard masks on gates in semiconductor manufacturing process 有权
标题翻译：在半导体制造工艺中去除门上的硬掩模的方法
公开(公告)号：US08796084B2
公开(公告)日：2014-08-05
申请号：US12776011
申请日：2010-05-07
申请人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
发明人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
IPC分类号： H01L21/8238 , H01L21/311 , H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/82385 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards.
摘要翻译：如下进行半导体制造工序中的门上去除硬掩模的方法。首先，在半导体衬底上形成具有硬掩模的第一栅极和第二栅极，其中第二栅极大于第一栅极。第一栅极和第二栅极可以与硅 - 锗（SiGe）源极和漏极区域相关联以形成p型晶体管。接下来，沉积光致抗蚀剂层，并且在第二栅极的硬掩模上形成光致抗蚀剂层的开口。然后，通过蚀刻完全去除第一和第二栅极上的光致抗蚀剂层。因为没有光致抗蚀剂残留物，所以第一和第二栅极上的硬掩模可以被完全去除。

126. 发明授权

US08598630B2 Photo alignment mark for a gate last process 有权
标题翻译：最后一个进程的照片对齐标记
公开(公告)号：US08598630B2
公开(公告)日：2013-12-03
申请号：US12470333
申请日：2009-05-21
申请人： Gary Shen , Ming-Yuan Wu , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang
发明人： Gary Shen , Ming-Yuan Wu , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L23/52
CPC分类号： H01L23/544 , H01L21/31051 , H01L21/823828 , H01L23/585 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，第一和第二区域彼此隔离，形成在第一区域中的多个晶体管，形成在第二区域中的对准标记，对准标记具有在第一方向上的多个有效区域，以及形成在所述对准标记上的伪栅极结构，所述伪栅极结构在与所述第一方向不同的第二方向上具有多条线。

127. 发明授权

US08552522B2 Dishing-free gap-filling with multiple CMPs 有权
公开(公告)号：US08552522B2
公开(公告)日：2013-10-08
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/70
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

128. 发明授权

US08390072B2 Chemical mechanical polishing (CMP) method for gate last process 有权
标题翻译：门最后工艺的化学机械抛光（CMP）方法
公开(公告)号：US08390072B2
公开(公告)日：2013-03-05
申请号：US13156558
申请日：2011-06-09
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

129. 发明授权

US08372706B2 Semiconductor device fabrication method including hard mask and sacrificial spacer elements 有权
标题翻译：包括硬掩模和牺牲隔离元件的半导体器件制造方法
公开(公告)号：US08372706B2
公开(公告)日：2013-02-12
申请号：US13218720
申请日：2011-08-26
申请人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.
摘要翻译：提供一种制造半导体器件的方法。在基板上形成第一硬掩模层。第二硬掩模层形成覆盖在第一硬掩模层上的基板。通过使用第一和第二硬掩模层中的至少一个来在衬底上形成伪栅极结构，以对虚拟栅极结构进行图案化。在虚拟栅极结构附近形成间隔元件。邻近衬垫元件的衬底上的应变区域（例如，邻接间隔元件）。然后在形成应变区域之后去除第二硬掩模层和间隔元件。

130. 发明授权

US08361866B2 Modifying work function in PMOS devices by counter-doping 有权
公开(公告)号：US08361866B2
公开(公告)日：2013-01-29
申请号：US13204461
申请日：2011-08-05
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8234
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

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