专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明申请

US20120132885A1 Fabrication of Graphene Electronic Devices Using Step Surface Contour 有权
标题翻译：使用阶梯面轮廓制造石墨烯电子器件
公开(公告)号：US20120132885A1
公开(公告)日：2012-05-31
申请号：US13306031
申请日：2011-11-29
申请人： Gunther LIPPERT , Jaroslaw Dabrowski , Grzegorz Lupina , Olaf Seifarth
发明人： Gunther LIPPERT , Jaroslaw Dabrowski , Grzegorz Lupina , Olaf Seifarth
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/02527 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L29/1606 , H01L29/772 , H01L29/7781 , H01L29/78
摘要： A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.
摘要翻译：一种制造电子部件的方法，包括提供基板; 并沉积石墨烯层; 其中所述基板设置有范德华功能层，或者在沉积所述石墨烯层之前在所述基板上沉积范德华功能层; 形成表面台阶轮廓; 并且石墨烯层的生长以阶梯轮廓种植。

122. 发明申请

US20120001192A1 BIPOLAR TRANSISTOR HAVING SELF-ADJUSTED EMITTER CONTACT 有权
标题翻译：具有自调节发射体接触的双极晶体管
公开(公告)号：US20120001192A1
公开(公告)日：2012-01-05
申请号：US12998869
申请日：2009-12-03
申请人： Alexander Fox , Bernd Heinemann , Steffen Marschmeyer
发明人： Alexander Fox , Bernd Heinemann , Steffen Marschmeyer
IPC分类号： H01L29/70 , H01L21/331
CPC分类号： H01L29/66242 , H01L21/8222 , H01L21/8249 , H01L29/0804 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/161 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.
摘要翻译：一种半导体器件，包括由第一导电类型的半导体材料制成并具有第一绝缘区域的衬底层和垂直双极晶体管，其具有由第二导电类型的单晶半导体材料制成的集电体的第一垂直部分，并且被布置在第一绝缘区域的开口中，第二绝缘区域部分地位于集电器的第一垂直部分上并且部分地位于第一绝缘区域上并且在集电器的区域中具有开口，其中开口的第二垂直部分设置由单晶材料构成的集电体，所述部分包括第二导电类型的内部区域，由第一导电类型的单晶半导体材料制成的基底，在横向方向上围绕基底的基极连接区域，T形发射极由第二导电类型的半导体材料制成并与基底连接重叠其中基底连接区域除了与基底相邻的晶种层或邻近基极接触处的金属化层组成，其半导体材料的化学成分不同于集电极，基极和发射极的半导体材料并且其中第一导电类型的多数电荷载流子具有比其更大的迁移率。

123. 发明授权

US07855404B2 Bipolar complementary semiconductor device 有权
标题翻译：双极互补半导体器件
公开(公告)号：US07855404B2
公开(公告)日：2010-12-21
申请号：US10581127
申请日：2004-12-01
申请人： Bernd Heinenman , Jürgen Drews , Steffen Marschmayer , Holger Rücker
发明人： Bernd Heinenman , Jürgen Drews , Steffen Marschmayer , Holger Rücker
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0826
摘要： A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.
摘要翻译：互补BiCMOS半导体器件包括第一导电类型的衬底和设置在其中的多个有源区，并且通过浅场绝缘区在横向上限定，其中布置有具有外延基底的垂直npn双极晶体管在有源区的第一子数目和具有外延基极的垂直pnp双极晶体管布置在有源区的第二子数目中，其中一个晶体管类型或两个晶体管类型都具有集电极区和集电极接触区同一个相同的活跃区域。为了提高专用于基板的导电类型与集电极区域的导电类型相同的第一晶体管类型的高频特性，在集电极区域和基板之间设置绝缘掺杂区域。

124. 发明授权

US07777255B2 Bipolar transistor with raised base connection region and process for the production thereof 有权
标题翻译：具有凸起基极连接区域的双极晶体管及其制造方法
公开(公告)号：US07777255B2
公开(公告)日：2010-08-17
申请号：US10580669
申请日：2004-12-03
申请人： Holger Rücker , Bernd Heinemann
发明人： Holger Rücker , Bernd Heinemann
IPC分类号： H01L31/072
CPC分类号： H01L29/66287 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion. The lateral extent of the spacer increases from its interface with respect to the base layer with increasing height above the base layer, wherein a first interface formed by the emitter and the spacer meets a second interface formed by the emitter and the inner base portion at a first angle which is either a right angle or an obtuse angle, and a third interface formed by the spacer and the outer base portion meets the second interface at a second obtuse angle which is larger than the first angle.
摘要翻译：双极晶体管具有基底，其具有外延基底层和凸起的基底连接区域，该基底连接区域在与衬底表面平行的方向上包围由绝缘材料的隔离物围绕的发射器。外延基层在与基板表面垂直的高度方向上升高。通过绝缘材料的间隔件将T形横截面轮廓的发射器从外部基部侧向分开。其T形的垂直杆的下端与内部基部相邻。间隔物的横向范围从其相对于基底层的界面增加，其高度高于基底层，其中由发射体和间隔物形成的第一界面与由发射体和内部基底部分形成的第二界面在第一角度是直角或钝角，并且由间隔件和外基部形成的第三界面以大于第一角度的第二钝角与第二界面相交。

125. 发明授权

US07714420B2 Apparatus for contactlessly coupling chips 有权
标题翻译：用于非接触地耦合芯片的装置
公开(公告)号：US07714420B2
公开(公告)日：2010-05-11
申请号：US10577114
申请日：2004-10-28
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H01L23/48 , G08C17/00 , H04B5/00
CPC分类号： H04B5/0012 , H01L23/48 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2924/3011
摘要： A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.
摘要翻译：一种芯片装置，包括具有至少一个第一信号接口的第一芯片，所述第一信号接口具有沿着第一数字密度的第一线布置的第一耦合元件，以及具有至少一个第二信号接口的至少一个第二信号接口，所述第二信号接口具有沿着第二线在第二数量密度中，其中第一和第二耦合元件允许在第一和第二信号接口之间的非接触信号传输，其中两个芯片彼此相对布置，第一和第二信号接口的耦合元件可以非接触地传输信号彼此之间，其中沿着与其相关联的线的至少一个信号接口的纵向范围大于两个纵向范围的重叠的长度，并且其中一个信号接口具有较大数量的耦合元件密度比其他。

126. 发明授权

US07606852B2 CORDIC unit 失效
标题翻译： CORDIC单位
公开(公告)号：US07606852B2
公开(公告)日：2009-10-20
申请号：US10498707
申请日：2002-12-20
申请人： Koushik Maharatna , Eckhard Grass , Banerjee Swapna , Dhar Anindya Sundar
发明人： Koushik Maharatna , Eckhard Grass , Banerjee Swapna , Dhar Anindya Sundar
IPC分类号： G06F17/16
CPC分类号： G06F7/5446
摘要： A CORDIC unit for the iterative approximation of a vector rotation through a rotary angle θ by a number of elementary rotations through elementary angles αi, including elementary rotation stages for respectively affecting an elementary rotation through an elementary angle αi as an iteration step in the iterative approximation. After such an elementary rotation there remains a residual angle through which rotation is still to be affected. The elementary rotation stages of the CORDIC unit are adapted for rotation through elementary angles αi given by powers of two with a negative integral exponent. The CORDIC unit can also include a triggering device for triggering the elementary rotations, a triggering device which is adapted prior to each iteration step to compare the residual angle to at least one of the elementary angles and to omit those elementary rotation stages whose elementary angles are greater than the residual angle.
摘要翻译： CORDIC单元，用于通过旋转角度θ向量旋转迭代近似通过基本角度α的基本旋转，包括用于分别影响通过基本角度的基本旋转的基本旋转阶段作为迭代近似中的迭代步骤。在这样的基本旋转之后，仍然存在一个剩余角度，旋转仍然受到影响。 CORDIC单元的基本旋转级适于通过具有负整数指数的两个功率给出的基本角度alphai进行旋转。 CORDIC单元还可以包括用于触发基本旋转的触发装置，触发装置，其在每个迭代步骤之前被适配以将残余角度与至少一个基本角度进行比较，并且省略基本角度为大于剩余角度。

127. 发明授权

US07595534B2 Layers in substrate wafers 有权
标题翻译：衬底晶圆层
公开(公告)号：US07595534B2
公开(公告)日：2009-09-29
申请号：US10433969
申请日：2001-12-06
申请人： Bernd Heinemann , Karl-Ernst Ehwald , Dieter Knoll , Bernd Tillack , Dirk Wolansky , Peter Schley
发明人： Bernd Heinemann , Karl-Ernst Ehwald , Dieter Knoll , Bernd Tillack , Dirk Wolansky , Peter Schley
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/74 , H01L21/26506 , H01L21/823807 , H01L21/823892 , H01L29/1083
摘要： The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.
摘要翻译：本发明涉及衬底晶片中的层。本发明的目的是提供衬底晶片中的层，其中克服了常规组件的缺点，以便一方面实现具有相对较低成本的高度缩放的数字CMOS电路中的闩锁的适当电阻，以及另一方面，为了确保模拟高频电路的低衬底损耗/耦合，此外，以非破坏性的方式影响组件行为。为此，本发明提供了在具有一个或多个掩埋的高碳Si层（3）的外延层和Si覆盖层（4）下的高电阻p-Si衬底（2）中的注入剂量，与传统的基板晶片相比，通过抑制掺杂剂扩散以及在补偿注入缺陷时产生缺陷而用于逆向槽型材，从而实现了谷电阻的降低，最后增加了电阻闭锁

128. 发明授权

US07583770B2 Multiplex signal error correction method and device 失效
标题翻译：多路复用信号纠错方法及装置
公开(公告)号：US07583770B2
公开(公告)日：2009-09-01
申请号：US10530595
申请日：2003-10-09
申请人： Alfonso Troya , Milos Krstic , Koushik Maharatna
发明人： Alfonso Troya , Milos Krstic , Koushik Maharatna
IPC分类号： H04L7/00
CPC分类号： H04L25/0204 , H04L25/022 , H04L27/2657 , H04L27/2675 , H04L2025/03414
摘要： A method of reducing a phase error caused by a plurality of error sources in a signal in the form of a sequence of a plurality of digital partial signals associated with a number of subcarriers (k) of a carrier, the method including, for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. One embodiment provides the equalization with elimination of an accumulation of a phase error over the sequence of the partial signals. In addition the estimation includes detecting a plurality of predetermined pilot signals and determining a phase correction factor on the basis of the detected pilot signals, with at least one multiplication operation carried out solely by means of shift and adding operations. A corresponding apparatus is also described.
摘要翻译：一种减少由与载波的多个子载波（k）相关联的多个数字部分信号的序列形式的信号中的多个误差源引起的相位误差的方法，所述方法包括：对于每个部分信号：部分信号（Y（i，k））的均衡，均衡部分信号（X（i，k））的相位误差的估计以及均衡部分信号的估计相位误差的校正。一个实施例提供了均衡，消除了部分信号的序列上的相位误差的积累。此外，估计包括检测多个预定导频信号，并且基于检测到的导频信号确定相位校正因子，其中仅通过移位和相加操作进行至少一次乘法运算。还描述了相应的装置。

129. 发明授权

US07244667B2 Method and device for the production of thin epitaxial semiconductor layers 有权
标题翻译：用于生产薄外延半导体层的方法和装置
公开(公告)号：US07244667B2
公开(公告)日：2007-07-17
申请号：US10484975
申请日：2002-07-25
申请人： Bernd Tillack , Dirk Wolansky , Georg Ritter , Thomas Grabolla
发明人： Bernd Tillack , Dirk Wolansky , Georg Ritter , Thomas Grabolla
IPC分类号： H01L21/205
CPC分类号： H01L21/02529 , C23C16/0218 , C23C16/54 , H01L21/02532 , H01L21/0262 , H01L21/02658
摘要： System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput.The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.
摘要翻译：用于制造扩散抑制外延半导体层的系统，通过该系统，可以在大的半导体衬底上以高通量产生薄的扩散抑制性外延半导体层。首先清洁待涂覆的半导体衬底的表面，然后将衬底在低压间歇反应器中加热到第一温度（预烘烤温度）。待涂覆的表面接下来在第一反应器压力下进行氢预烘烤操作。在下一步骤中，将半导体衬底在低压热或温壁间歇反应器中加热到低于第一温度的第二温度（沉积温度），并且在达到热力学平衡条件之后，沉积扩散抑制半导体层在高于等于或低于第一反应器压力的第二反应器压力下在化学气相沉积工艺（CVD）中待涂覆的表面上。

130. 发明授权

US07205188B2 Method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip 失效
标题翻译：在芯片上制造高速垂直npn双极晶体管和互补MOS晶体管的方法
公开(公告)号：US07205188B2
公开(公告)日：2007-04-17
申请号：US10450006
申请日：2001-12-06
申请人： Dieter Knoll , Bernd Heinemann
发明人： Dieter Knoll , Bernd Heinemann
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249
摘要： The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.
摘要翻译：本发明涉及在芯片上制造高速垂直npn双极晶体管和互补MOS晶体管的方法。为了在芯片上生产这些高速垂直npn双极晶体管和互补MOS晶体管，所有技术方法步骤用于在npn双极晶体管的有源区中产生集电极，基极和发射极的垂直结构以及横向构成集电极区域之前，在产生用于MOS晶体管的槽和栅极绝缘层之前执行基极区域和发射极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式