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111. 发明公开

EP0209198A2 Schaltungsanordnung für ein Farbbildaufzeichungs- und Wiedergabegerät oder einen Farbfernsehempfänger 失效
标题翻译：用于Farbbildaufzeichungs-电路装置和再现装置或彩色电视接收机。
公开(公告)号：EP0209198A2
公开(公告)日：1987-01-21
申请号：EP86201235.8
申请日：1986-07-15
申请人： Philips Patentverwaltung GmbH , Philips Electronics N.V.
发明人： Wölber, Jörg , Gedl, Karl
IPC分类号： H04N9/45
CPC分类号： H04N9/455 , H04N9/84 , H04N9/898
摘要： Die Erfindung betrifft eine Schaltungsanordnung für ein Farbbildaufzeichnungs- und Wiedergabegerät oder einen Farbfernsehempfänger. Solche Geräte weisen einen Phasenregelkreis auf, in dem ein Oszillator (18, 59) entsprechend dem in einer Phasenvergleichsschaltung (9,40) stattfindenden Phasenvergleich zwischen Farbsynchronsignal und einem Vergleichssignal gesteuert wird. Das Steuersignal wird wenigstens zwei nacheinander und zyklisch umschaltbaren Abtast- und Haltegliedern (12, 13; 49 bis 52) zugeführt. Diese tasten das Steuersignal während der Farbsynchronaustastzeit ab. Die Ausgangssignale der Abtast-und Halteglieder (12, 13; 49 bis 52) werden einem Addierer (16, 54) zugeführt, der mit dem Oszillator (18, 59) gekoppelt ist. Dadurch mitteln sich z.B. die dem Steuersignal überlagerten durch die PAL-Umschaltung bedingten Störsignale heraus.
摘要翻译：用于彩色图象记录和再现设备（VCR）或一个彩色电视接收机的电路装置。搜索设备具有其中相位调整电路的振荡器（18，59）被控制在雅舞的色同步信号，并在相位比较器电路（9，40）所执行的基准信号之间的相位比较。从相位比较电路的控制信号被施加到的至少两个扫描和锁定单元（12，13; 49〜52），其可以连续地循环地改变过来。这些单元中的色同步消隐时间期间扫描控制信号。扫描和锁定单元的输出信号（12，13; 49〜52）在加法器（16，54）耦合到所述振荡器（18，59）被施加到。从PAL转换所产生的并叠加在控制信号中的干扰信号因此被消除。

112. 发明公开

EP0175434A2 Apparatus for generating television synchronizing signals 失效
标题翻译：用于产生电视同步信号的装置。
公开(公告)号：EP0175434A2
公开(公告)日：1986-03-26
申请号：EP85302663.1
申请日：1985-04-16
申请人： AMPEX CORPORATION
发明人： Luke, Rylan D.
IPC分类号： H04N9/45
CPC分类号： H04N9/45
摘要： A signal generator for generating a clocked PAL reference video signal from a single signal source. A counter-divider (30) extracts subcarrier frequency component from the PAL reference video signal and a frequency changer (34) in combination with a counter-divider (38) extracts a horizontal frequency component from the PAL reference video signal.

113. 发明公开

EP0145224A1 Stabilized color television subcarrier regenerator circuit and method 失效
标题翻译：稳定化的彩色副载波再生器电路和方法。
公开(公告)号：EP0145224A1
公开(公告)日：1985-06-19
申请号：EP84307485.7
申请日：1984-10-31
申请人： SONY CORPORATION
发明人： Quan, Ronald
IPC分类号： H04N9/45 , H03L7/00
CPC分类号： H04N9/45
摘要： A subcarrier regenerator circuit for use in color television receiver demodulators. The regenerator includes a voltage-controlled oscillator and a fixed frequency oscillator set to the nominal subcarrier frequency. During the vertical retrace period, a phase detector forces the output of the voltage-controlled oscillator to match that of the fixed-frequency oscillator. The output of the detector is also stored. During the active vertical scan, the phase detector compares the voltage-controlled oscillator output with the color burst synchronization signal and produces an output which is added with the stored output. The added signal is used to adjust the output of the voltage-controlled oscillator to match the color burst signal in phase and frequency, so that the output can be used by the synchronous color signal demodulators.

114. 发明公开

EP3157254A4 SOLID-STATE IMAGE CAPTURING DEVICE AND IMAGE CAPTURING METHOD 无效
公开(公告)号：EP3157254A4
公开(公告)日：2018-03-21
申请号：EP15806766
申请日：2015-06-08
申请人： OLYMPUS CORP
发明人： MIZUNO KYOSUKE , KOMINE HITOSHI , FUJISAWA YUTAKA , FUJIMOTO TAKEHIDE , KATO HIDEKI , TOMURA SADAAKI , UBAYAMA NANAKO
IPC分类号： H04N9/09 , A61B1/04 , G02B23/24 , H04N5/225 , H04N5/343 , H04N5/345 , H04N5/351 , H04N5/77 , H04N9/04 , H04N9/45 , H04N9/797 , H04N9/804
CPC分类号： H04N9/045 , G02B23/2484 , H04N5/2351 , H04N5/343 , H04N5/345 , H04N5/3452 , H04N5/351 , H04N5/77 , H04N5/772 , H04N9/09 , H04N9/797 , H04N9/8042 , H04N2005/2255
摘要： A solid-state imaging apparatus (100) includes an imaging unit (222) that images a subject to generate a plurality of pieces of image data having information corresponding to different types of color components at same pixel positions, an operation mode setting unit (5101) that sets an operation mode of the imaging unit, a thinning rate setting unit (5102) that sets a thinning rate relative to each of the plurality of pieces of image data of the different types of color components in accordance with the operation mode, a thinning processor (262) that performs thinning processing relative to each of the plurality of pieces of image data of the different types of color components generated by the imaging unit (222) in accordance with the thinning rate, and a transmission unit (502) that transmits the plurality of pieces of image data of different types of color components subjected to the thinning processing.

115. 发明授权

EP0767589B1 Clock signal generator 失效
标题翻译：时钟信号发生器
公开(公告)号：EP0767589B1
公开(公告)日：2007-11-07
申请号：EP96304876.4
申请日：1996-07-02
申请人： SAMSUNG ELECTRONICS CO. LTD.
发明人： Kim, Young-Chul
IPC分类号： H04N9/45
CPC分类号： H04N9/45

116. 发明授权

EP1269759B1 VERFAHREN UND VORRICHTUNG ZUM ERZEUGEN EINES MIT EINEM REFERENZSIGNAL VERKOPPELTEN TAKTSIGNALS 有权
标题翻译：方法和装置用于产生参考的信号耦合的时钟信号
公开(公告)号：EP1269759B1
公开(公告)日：2007-05-09
申请号：EP01925493.7
申请日：2001-03-20
申请人： Micronas GmbH
发明人： SCHOENE, Andreas , BEINTKEN, Hartmut
IPC分类号： H04N9/64 , H04N5/12 , H04N9/45
CPC分类号： H04N9/64 , H04N5/126 , H04N9/45
摘要： In order to generate a clock signal (fT1) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (fT1) is generated from a high-frequency clock pulse (f0) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (fT1) is generated from the high-frequency clock pulse (f0), and the phase deviation between the first clock pulse (fT2) and the second clock pulse (fT1) is determined. The digitized sampling values of the reference signal (FBAS) that have the clock frequency (fT2) are converted, according to the determined phase deviation, into corresponding digitized sampling values having the second clock frequency (fT1) and are used as a setpoint selection for generating the second clock pulse (fT1) thus coupled to the reference signal.

117. 发明授权

EP0906701B1 COLOR DEMODULATION USING DIGITAL AND ANALOG CIRCUITS 失效
标题翻译：具有数字和模拟电路彩色解调
公开(公告)号：EP0906701B1
公开(公告)日：2006-11-15
申请号：EP98904328.6
申请日：1998-03-05
申请人： Koninklijke Philips Electronics N.V.
发明人： WISSING, Roy, Wilhelmus, Bernardus , VAN LAMMEREN, Johannes, Petrus, Maria , PELGROM, Marcellinus, Johannes, Maria
IPC分类号： H04N9/44 , H04N9/45 , H04N9/64 , H04N11/16 , H04N11/14
CPC分类号： H04N9/66 , H04N9/45 , H04N11/14 , H04N11/16
摘要： In a method of demodulating an analog chrominance signal (C), digital quadrature signals are generated (DPA, SIN ROM, COS ROM) for demodulating (MUL DAC U, MUL DAC V) the analog chrominance signal (C) to obtain analog demodulated color difference signals (U, V). A digital phase error signal is furnished (ΣΔ mod) from at least one (V) of the analog demodulated color difference signals (U, V). The digital phase error signal is digitally filtered (DLF) to obtain a phase control signal (K) for the digital quadrature signals generation (DPA, SIN ROM, COS ROM).

118. 发明公开

EP0913947A3 Phase-locked loop 审中-公开
标题翻译：锁相环
公开(公告)号：EP0913947A3
公开(公告)日：2003-09-10
申请号：EP98308956.6
申请日：1998-11-02
申请人： Texas Instruments Incorporated
发明人： Chang, Peter , Renner, Karl
IPC分类号： H03L7/08 , H04N9/45 , H03L7/099
CPC分类号： H04N9/45 , H03L7/087 , H03L7/0994
摘要： A phase-locked loop 302 for maintaining the lock of an oscillator 202 with a color burst of a composite video signal. The PLL 302 comprises an oscillator 202 for receiving a pixel clock PCK at a pixel clock frequency f pix , and for converting the pixel clock PCK to a color sub-carrier frequency f sc ; a multiplier 206 for multiplying composite video pixels comprised in said composite video signal by samples stored in a memory 204 at said sub-carrier frequency; a register 212 for receiving an output from said multiplier 206 and for calculating a color burst phase error; a processor 2 for receiving the color burst phase error and for providing an increment signal inc sc to the oscillator 202 in response thereto, said oscillator 202 being incremented by an amount to substantially drive the phase error to zero.
摘要翻译：锁相环302，用于用复合视频信号的色同步保持振荡器202的锁定。 PLL 302包括用于以像素时钟频率fpix接收像素时钟PCK并将像素时钟PCK转换为彩色副载波频率fsc的振荡器202; 乘法器206，用于将所述复合视频信号中包含的复合视频像素乘以在所述副载波频率处存储在存储器204中的样本; 寄存器212，用于接收来自所述乘法器206的输出并计算色同步相位误差; 处理器2，用于接收色同步相位误差，并响应于此向振荡器202提供增量信号incs，所述振荡器202递增一定量以实质上驱动相位误差为零。

119. 发明公开

EP0855802A3 PLL circuit and phase lock detector 失效
标题翻译： Phasenregelkreisschaltung und Phasenverriegelungsdetektor
公开(公告)号：EP0855802A3
公开(公告)日：2001-01-17
申请号：EP98300353.4
申请日：1998-01-19
申请人： SANYO ELECTRIC Co., Ltd.
发明人： Kiyose, Masashi , Ito, Hiroya
IPC分类号： H03L7/089 , H03L7/095 , H04N9/45 , H03L7/10
CPC分类号： H03L7/0997 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/10 , H03L7/107 , H04N9/45 , H04N11/146
摘要： A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation clock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.
摘要翻译：电路具有连接在两个电荷泵电路和压控振荡器（107）之间的低通滤波器（30），以平滑泵电路的输出。锁定检测器检测振荡时钟是否相对于参考时钟相位保持恒定的相位差。当振荡时钟保持/不保持恒定的相位差时，选择电路操作各个泵电路。还包括用于产生色度信息和亮度信息的图像信号处理装置的独立权利要求。

120. 发明授权

EP0461896B1 Digital signal processing system 失效
标题翻译：数字信号处理系统
公开(公告)号：EP0461896B1
公开(公告)日：1997-11-12
申请号：EP91305350.0
申请日：1991-06-13
申请人： QUESTECH LIMITED
发明人： Tyson, Peter
IPC分类号： H04N9/64 , H04N9/45
CPC分类号： H04N9/64

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