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1. 发明公开

EP0913947A2 Phase-locked loop 审中-公开
标题翻译： Phasenregelkreis
公开(公告)号：EP0913947A2
公开(公告)日：1999-05-06
申请号：EP98308956.6
申请日：1998-11-02
申请人： Texas Instruments Incorporated
发明人： Chang, Peter , Renner, Karl
IPC分类号： H03L7/08
CPC分类号： H04N9/45 , H03L7/087 , H03L7/0994
摘要： A phase-locked loop 302 for maintaining the lock of an oscillator 202 with a color burst of a composite video signal. The PLL 302 comprises an oscillator 202 for receiving a pixel clock PCK at a pixel clock frequency f pix , and for converting the pixel clock PCK to a color sub-carrier frequency f sc ; a multiplier 206 for multiplying composite video pixels comprised in said composite video signal by samples stored in a memory 204 at said sub-carrier frequency; a register 212 for receiving an output from said multiplier 206 and for calculating a color burst phase error; a processor 2 for receiving the color burst phase error and for providing an increment signal inc sc to the oscillator 202 in response thereto, said oscillator 202 being incremented by an amount to substantially drive the phase error to zero.
摘要翻译：锁相环302，用于利用复合视频信号的色同步信号来保持振荡器202的锁定。 PLL 302包括用于以像素时钟频率fpix接收像素时钟PCK并将像素时钟PCK转换为彩色副载波频率fsc的振荡器202; 乘法器206，用于将包含在所述复合视频信号中的复合视频像素乘以存储在存储器204中的所述副载波频率的样本; 寄存器212，用于接收来自所述乘法器206的输出并用于计算色同步相位误差; 处理器2，用于接收彩色同步相位误差，并响应于此向振荡器202提供增量信号incsc，所述振荡器202递增一个量，以将相位误差基本上驱动到零。

2. 发明公开

EP0913947A3 Phase-locked loop 审中-公开
标题翻译：锁相环
公开(公告)号：EP0913947A3
公开(公告)日：2003-09-10
申请号：EP98308956.6
申请日：1998-11-02
申请人： Texas Instruments Incorporated
发明人： Chang, Peter , Renner, Karl
IPC分类号： H03L7/08 , H04N9/45 , H03L7/099
CPC分类号： H04N9/45 , H03L7/087 , H03L7/0994
摘要： A phase-locked loop 302 for maintaining the lock of an oscillator 202 with a color burst of a composite video signal. The PLL 302 comprises an oscillator 202 for receiving a pixel clock PCK at a pixel clock frequency f pix , and for converting the pixel clock PCK to a color sub-carrier frequency f sc ; a multiplier 206 for multiplying composite video pixels comprised in said composite video signal by samples stored in a memory 204 at said sub-carrier frequency; a register 212 for receiving an output from said multiplier 206 and for calculating a color burst phase error; a processor 2 for receiving the color burst phase error and for providing an increment signal inc sc to the oscillator 202 in response thereto, said oscillator 202 being incremented by an amount to substantially drive the phase error to zero.
摘要翻译：锁相环302，用于用复合视频信号的色同步保持振荡器202的锁定。 PLL 302包括用于以像素时钟频率fpix接收像素时钟PCK并将像素时钟PCK转换为彩色副载波频率fsc的振荡器202; 乘法器206，用于将所述复合视频信号中包含的复合视频像素乘以在所述副载波频率处存储在存储器204中的样本; 寄存器212，用于接收来自所述乘法器206的输出并计算色同步相位误差; 处理器2，用于接收色同步相位误差，并响应于此向振荡器202提供增量信号incs，所述振荡器202递增一定量以实质上驱动相位误差为零。

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