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111. 发明授权

US07915124B2 Method of forming dielectric layer above floating gate for reducing leakage current 有权
标题翻译：在浮栅上形成介质层以减少漏电流的方法
公开(公告)号：US07915124B2
公开(公告)日：2011-03-29
申请号：US12170321
申请日：2008-07-09
申请人： James K. Kai , Dana Lee , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis , Henry Chin
发明人： James K. Kai , Dana Lee , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis , Henry Chin
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273
摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.
摘要翻译：公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。该方法包括形成具有顶部和至少两个侧面的浮动栅极。在浮动栅极的顶部形成介电盖。在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

112. 发明授权

US07894263B2 High voltage generation and control in source-side injection programming of non-volatile memory 有权
标题翻译：非易失性存储器的源侧注入编程中的高压发生和控制
公开(公告)号：US07894263B2
公开(公告)日：2011-02-22
申请号：US11864825
申请日：2007-09-28
申请人： Dana Lee , Hock So
发明人： Dana Lee , Hock So
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C2211/565
摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.
摘要翻译：使用源侧热电子注入编程非易失性存储器。为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。在充电之后，将第二低电压施加到与选定位线相邻的未选位线。由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

113. 发明授权

US07869273B2 Reducing the impact of interference during programming 有权
标题翻译：减少编程过程中的干扰影响
公开(公告)号：US07869273B2
公开(公告)日：2011-01-11
申请号：US11849992
申请日：2007-09-04
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

114. 发明申请

US20100259989A1 OFFSET NON-VOLATILE STORAGE 有权
公开(公告)号：US20100259989A1
公开(公告)日：2010-10-14
申请号：US12822584
申请日：2010-06-24
申请人： Jeffrey W. Lutze , Dana Lee
发明人： Jeffrey W. Lutze , Dana Lee
IPC分类号： G11C16/04
CPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/11568 , H01L27/1157
摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

115. 发明授权

US07808839B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US07808839B2
公开(公告)日：2010-10-05
申请号：US11810714
申请日：2007-06-06
申请人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
发明人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。在第一区域和第二区域之间限定连续的第一通道区域。多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

116. 发明申请

US20100006915A1 DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT 有权
标题翻译：用于降低泄漏电流的浮动门上的介电层
公开(公告)号：US20100006915A1
公开(公告)日：2010-01-14
申请号：US12170327
申请日：2008-07-09
申请人： Dana Lee , Henry Chin , James K. Kai , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis
发明人： Dana Lee , Henry Chin , James K. Kai , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/84 , H01L27/1203
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.
摘要翻译：公开了一种包括一组非易失性存储元件的存储器系统。给定的存储单元在浮动栅极上方具有电介质盖。在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。电介质盖减少了浮动栅极和控制栅极之间的漏电流。电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

117. 发明申请

US20090323429A1 PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 有权
标题翻译：使用最小额外罚款减少差距的编程算法
公开(公告)号：US20090323429A1
公开(公告)日：2009-12-31
申请号：US12163073
申请日：2008-06-27
申请人： Dana Lee , Deepanshu Dutta , Yingda Dong
发明人： Dana Lee , Deepanshu Dutta , Yingda Dong
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

118. 发明申请

US20090080263A1 REDUCING PROGRAMMING VOLTAGE DIFFERENTIAL NONLINEARITY IN NON-VOLATILE STORAGE 有权
标题翻译：降低非易失性存储中的编程电压差异非线性
公开(公告)号：US20090080263A1
公开(公告)日：2009-03-26
申请号：US11861909
申请日：2007-09-26
申请人： Dana Lee , Jun Wan
发明人： Dana Lee , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C29/00
摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.
摘要翻译：采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

119. 发明授权

US07468918B2 Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data 有权
标题翻译：用于通过消除对字线数据的预充电依赖来减少编程干扰的非易失性存储器编程系统
公开(公告)号：US07468918B2
公开(公告)日：2008-12-23
申请号：US11618594
申请日：2006-12-29
申请人： Yingda Dong , Jeffrey W. Lutze , Dana Lee , Gerrit Jan Hemink
发明人： Yingda Dong , Jeffrey W. Lutze , Dana Lee , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

120. 发明申请

US20080291735A1 METHOD FOR USING TRANSITIONAL VOLTAGE DURING PROGRAMMING OF NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储编程过程中使用过渡电压的方法
公开(公告)号：US20080291735A1
公开(公告)日：2008-11-27
申请号：US11753958
申请日：2007-05-25
申请人： Yingda Dong , Jeffrey W. Lutze , Dana Lee
发明人： Yingda Dong , Jeffrey W. Lutze , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10
摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.
摘要翻译：为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。在一个实施例中，第一中间幅度与升压电压相似或相同。第二中间幅度大于第一中间幅度，但小于第三幅度。这样的布置可以减少节目干扰的影响。

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