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1. 发明授权

US08184479B2 Reducing the impact of interference during programming 有权
公开(公告)号：US08184479B2
公开(公告)日：2012-05-22
申请号：US13221147
申请日：2011-08-30
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

2. 发明授权

US08094492B2 Reducing the impact of interference during programming 有权
标题翻译：减少编程过程中的干扰影响
公开(公告)号：US08094492B2
公开(公告)日：2012-01-10
申请号：US12962902
申请日：2010-12-08
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

3. 发明申请

US20110075477A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 有权
标题翻译：减少编程过程中干扰的影响
公开(公告)号：US20110075477A1
公开(公告)日：2011-03-31
申请号：US12962902
申请日：2010-12-08
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

4. 发明申请

US20090059660A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 有权
标题翻译：减少编程过程中干扰的影响
公开(公告)号：US20090059660A1
公开(公告)日：2009-03-05
申请号：US11849992
申请日：2007-09-04
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

5. 发明申请

US20110310671A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 有权
公开(公告)号：US20110310671A1
公开(公告)日：2011-12-22
申请号：US13221147
申请日：2011-08-30
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

6. 发明授权

US07869273B2 Reducing the impact of interference during programming 有权
标题翻译：减少编程过程中的干扰影响
公开(公告)号：US07869273B2
公开(公告)日：2011-01-11
申请号：US11849992
申请日：2007-09-04
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

7. 再颁专利

USRE43870E1 Reducing the impact of interference during programming 有权
公开(公告)号：USRE43870E1
公开(公告)日：2012-12-25
申请号：US13289108
申请日：2011-11-04
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

8. 发明申请

US20150058698A1 DATA RECOVERY FROM BLOCKS WITH GATE SHORTS 有权
标题翻译：数据恢复从块与短路
公开(公告)号：US20150058698A1
公开(公告)日：2015-02-26
申请号：US13974997
申请日：2013-08-23
申请人： Dana Lee , Abhijeet Manohar
发明人： Dana Lee , Abhijeet Manohar
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1068 , G06F11/1048 , G11C16/3431 , G11C29/00 , G11C29/50004 , G11C29/50008 , G11C2029/0411 , G11C2029/5002
摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.
摘要翻译：存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

9. 发明授权

US08953398B2 Block level grading for reliability and yield improvement 有权
标题翻译：块级分级可靠性和产量提高
公开(公告)号：US08953398B2
公开(公告)日：2015-02-10
申请号：US13527199
申请日：2012-06-19
申请人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
发明人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C29/56008 , G11C29/82 , G11C2029/4402
摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
摘要翻译：可以使用用于分级块的系统来改善存储器使用。诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

10. 发明申请

US20130128666A1 Scrub Techniques for Use with Dynamic Read 有权
标题翻译： Scrub技术用于动态阅读
公开(公告)号：US20130128666A1
公开(公告)日：2013-05-23
申请号：US13435476
申请日：2012-03-30
申请人： Chris Avila , Jianmin Huang , Dana Lee
发明人： Chris Avila , Jianmin Huang , Dana Lee
IPC分类号： G11C16/26
CPC分类号： G06F11/1048 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C2211/5634
摘要： The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.
摘要翻译：关于是否刷新或退出内存块的决定是基于正在使用的一组动态读取值。在使用动态读取值表的存储器系统中，该表被配置为包括如何处理读取错误（退出，刷新）以及不同动态读取情况的读取参数。在细化中，读取案例编号可用于为选择刷新或退出的块确定优先级。在读取擦除更精确的情况下，可以应用多个动态读取情况。此外，可以智能地选择应用哪些情况。

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