专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07894263B2 High voltage generation and control in source-side injection programming of non-volatile memory 有权
标题翻译：非易失性存储器的源侧注入编程中的高压发生和控制
公开(公告)号：US07894263B2
公开(公告)日：2011-02-22
申请号：US11864825
申请日：2007-09-28
申请人： Dana Lee , Hock So
发明人： Dana Lee , Hock So
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C2211/565
摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.
摘要翻译：使用源侧热电子注入编程非易失性存储器。为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。在充电之后，将第二低电压施加到与选定位线相邻的未选位线。由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

2. 发明申请

US20090086542A1 High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory 有权
标题翻译：非易失性存储器的源侧注入编程中的高压产生和控制
公开(公告)号：US20090086542A1
公开(公告)日：2009-04-02
申请号：US11864825
申请日：2007-09-28
申请人： Dana Lee , Hock So
发明人： Dana Lee , Hock So
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C2211/565
摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.
摘要翻译：使用源侧热电子注入编程非易失性存储器。为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。在充电之后，将第二低电压施加到与选定位线相邻的未选位线。由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

3. 发明授权

US08406052B2 High voltage generation and control in source-side injection programming of non-volatile memory 有权
标题翻译：非易失性存储器的源侧注入编程中的高压发生和控制
公开(公告)号：US08406052B2
公开(公告)日：2013-03-26
申请号：US13028847
申请日：2011-02-16
申请人： Dana Lee , Hock So
发明人： Dana Lee , Hock So
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C2211/565
摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.
摘要翻译：使用源侧热电子注入编程非易失性存储器。为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。在充电之后，将第二低电压施加到与选定位线相邻的未选位线。由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

4. 发明申请

US20110134694A1 High Voltage Generation And Control In Source-Side Injection Programming Of Non-Volatile Memory 有权
标题翻译：非易失性存储器的源侧注入编程中的高压发生和控制
公开(公告)号：US20110134694A1
公开(公告)日：2011-06-09
申请号：US13028847
申请日：2011-02-16
申请人： Dana Lee , Hock So
发明人： Dana Lee , Hock So
IPC分类号： G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C2211/565
摘要： Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.
摘要翻译：使用源侧热电子注入编程非易失性存储器。为了产生用于编程的高电压位线，对应于所选存储单元的位线使用第一低电压被充电到第一电平。在充电之后，将第二低电压施加到与选定位线相邻的未选位线。由于相邻位线与所选位线之间的电容耦合，所选择的位线通过将第二低电压施加到未选定的位线而升高到高于第一电压电平。用于这种存储器阵列的列控制电路不直接施加高电压，因此可被设计为承受较低的工作电压，允许使用低工作电压电路。

5. 发明申请

US20060256626A1 Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US20060256626A1
公开(公告)日：2006-11-16
申请号：US11460325
申请日：2006-07-27
申请人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
发明人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

6. 发明授权

US07447079B2 Method for sensing negative threshold voltages in non-volatile storage using current sensing 有权
标题翻译：使用电流检测来检测非易失性存储器中的负阈值电压的方法
公开(公告)号：US07447079B2
公开(公告)日：2008-11-04
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

7. 发明申请

US20050174844A1 Multi-bit-per-cell flash EEPROM memory with refresh 有权
标题翻译：多单元快闪EEPROM存储器刷新
公开(公告)号：US20050174844A1
公开(公告)日：2005-08-11
申请号：US11101938
申请日：2005-04-07
申请人： Hock So , Sau Wong
发明人： Hock So , Sau Wong
IPC分类号： G11C16/02 , B64C27/00 , G01N29/14 , G01N29/22 , G06F11/10 , G11C11/56 , G11C16/06 , G11C29/42 , G11C29/50 , G11C11/34
CPC分类号： G06F11/1072 , B64C27/006 , G01N29/14 , G01N29/227 , G06F11/106 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/04 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/00 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2211/5634
摘要： A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.
摘要翻译：多单元单元非易失性存储器将存储器单元的适当阈值电压划分为对应于用于存储数据的允许状态的范围和对应于指示数据错误的禁止区域的范围。读取过程自动检查阈值电压是否处于禁止区。在替代实施例中，刷新过程包括将阈值电压重新编程为允许状态。在闪速存储器的情况下，刷新读取存储器的扇区，并将来自扇区的校正数据保存在缓冲器或另一扇区中。来自缓冲器或其他扇区的校正数据可以被写回到原始扇区中，或者校正的数据可以留在另一扇区中，原始扇区的地址映射到另一个扇区。非易失性存储器的刷新过程可以响应于检测到禁止区域中的阈值电压而进行，作为存储器的加电过程的一部分，或者周期性地在几天，几周或几个月的周期内。作为另一方面，允许的状态对应于灰度编码数字值，使得在阈值电压中相邻的允许状态对应于仅在单个位中不同的多位值。错误检测和校正码可用于识别数据错误，并生成用于刷新操作的校正数据。

8. 发明授权

US07532516B2 Non-volatile storage with current sensing of negative threshold voltages 有权
标题翻译：具有电流检测负阈值电压的非易失性存储器
公开(公告)号：US07532516B2
公开(公告)日：2009-05-12
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

9. 发明授权

US07489554B2 Method for current sensing with biasing of source and P-well in non-volatile storage 有权
标题翻译：用于在非易失性存储器中源和P阱偏置的电流感测方法
公开(公告)号：US07489554B2
公开(公告)日：2009-02-10
申请号：US11771992
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.
摘要翻译：在用于非易失性存储元件的非易失性存储设备中执行电流检测。对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。感觉可以快速发生，因为等待地面反弹稳定没有延迟。

10. 发明申请

US20080247238A1 METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING 有权
标题翻译：使用电流感测感知非挥发性储存中的负压阈值电压的方法
公开(公告)号：US20080247238A1
公开(公告)日：2008-10-09
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/06 , G11C11/4091
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式