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101. 发明申请

US20110163416A1 METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES 有权
标题翻译：形成小尺寸电容器结构的方法
公开(公告)号：US20110163416A1
公开(公告)日：2011-07-07
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L29/92 , G06F19/00
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

102. 发明申请

US20100102433A1 APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER 审中-公开
标题翻译：用于半导体波浪处理的装置，用于从另一个另外的侧面移除单个半导体器件
公开(公告)号：US20100102433A1
公开(公告)日：2010-04-29
申请号：US12650179
申请日：2009-12-30
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L23/498
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/1191 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01032 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/29099 , H01L2924/00 , H01L2224/05099
摘要： A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.
摘要翻译：提供了在其基本上所有表面上具有钝化层以形成气密密封封装的芯片级或晶圆级封装。可以通过在半导体晶片的无源或背侧表面上设置第一钝化层来形成封装。半导体晶片可以附接到柔性膜并且例如通过晶片锯切割，以分离半导体器件。一旦切割，柔性膜可以被拉伸，以使各个半导体器件彼此横向移位并且基本上暴露其侧边缘。一旦半导体器件的侧边缘被暴露，就可以在器件的侧边缘和有源表面上形成钝化层。可以去除每个半导体器件的有源表面上的钝化层的一部分，以便暴露在其下形成的导电元件。

103. 发明授权

US07647886B2 Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers 失效
标题翻译：用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法
公开(公告)号：US07647886B2
公开(公告)日：2010-01-19
申请号：US10687458
申请日：2003-10-15
申请人： David J. Kubista , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Kevin L. Beaman , Er-Xuan Ping , Lingyi A. Zheng , Cem Basceri
发明人： David J. Kubista , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Kevin L. Beaman , Er-Xuan Ping , Lingyi A. Zheng , Cem Basceri
IPC分类号： C23C16/455 , C23C16/52 , C23F1/00 , H01L21/306 , C23C16/06 , C23C16/22
CPC分类号： C23C16/45544 , C23C16/4412 , Y10T137/0396
摘要： Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法在此公开。在一个实施例中，系统包括气相反应室，连接到反应室的第一排气管线，与第一排气管线流体连通的第一和第二阱，以及耦合到第一排气管线以除去气体的真空泵从反应室。第一和第二捕集器独立地可操作地单独地和/或共同地从反应室收集副产物。要强调的是提供本摘要以符合要求摘要的规则。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

104. 发明授权

US07625795B2 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US07625795B2
公开(公告)日：2009-12-01
申请号：US11217742
申请日：2005-09-01
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez , Er-Xuan Ping
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez , Er-Xuan Ping
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：集装箱电容器结构及其施工方法。蚀刻掩模和蚀刻用于暴露结构的电极（“底部电极”）的外表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，其可用于形成额外的电容。电容器电介质和顶电极分别形成在第一电极的内表面和外表面的两个部分上并与其相邻。第一电极和第二电极两者共同的表面积仅通过使用内表面增加，提供额外的电容而不减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。电容器电介质和第二电极部分的清除可以在衬底组件的上部位置进行，与在接触通孔的底部位置处的清除相反。

105. 发明授权

US07579235B2 Container capacitor structure and method of formation thereof 失效
公开(公告)号：US07579235B2
公开(公告)日：2009-08-25
申请号：US11545252
申请日：2006-10-10
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez , Er-Xuan Ping
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez , Er-Xuan Ping
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

106. 发明申请

US20090011540A1 DIE-WAFER PACKAGE AND METHOD OF FABRICATING SAME 有权
标题翻译： DIE-WAFER包装及其制造方法
公开(公告)号：US20090011540A1
公开(公告)日：2009-01-08
申请号：US12194261
申请日：2008-08-19
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/60
CPC分类号： H01L25/50 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05558 , H01L2224/1184 , H01L2224/13022 , H01L2224/13024 , H01L2224/13099 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06582 , H01L2924/00013 , H01L2924/01013 , H01L2924/01033 , H01L2924/01067 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/30107 , H01L2224/81 , H01L2224/29099
摘要： A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.
摘要翻译：晶片封装包括具有在第一表面上的第一多个接合焊盘和其第二相对表面上的第二多个接合焊盘的单片半导体管芯。第一和第二多个接合焊盘中的每一个包括凸块下金属化（UBM）层。单片化半导体管芯设置在半导体晶片的半导体管芯位置上，并且第一多个导电凸块将单片化半导体管芯的第一组接合焊盘与形成在半导体管芯部位上的第一组接合焊盘电耦合。第二组多个导电凸块设置在半导体管芯部位的第二组接合焊盘上。第三多个导电凸块设置在单片半导体管芯的第二多个接合焊盘上。第二和第三多个导电凸块被配置为与外部设备进行电互连。

107. 发明授权

US07344434B2 Retaining ring with shaped surface 有权
标题翻译：带环形表面的保持环
公开(公告)号：US07344434B2
公开(公告)日：2008-03-18
申请号：US10988211
申请日：2004-11-12
申请人： Hung Chih Chen , Steven M. Zuniga , Charles C. Garretson , Douglas R. McAllister , Stacy Meyer , Trung T. Doan , Daniel Cam Toan Lu , Romain Beau De Lamenie , Venkata R. Balagani , Aden Martin Allen , Michael Jon Fong
发明人： Hung Chih Chen , Steven M. Zuniga , Charles C. Garretson , Douglas R. McAllister , Stacy Meyer , Trung T. Doan , Daniel Cam Toan Lu , Romain Beau De Lamenie , Venkata R. Balagani , Aden Martin Allen , Michael Jon Fong
IPC分类号： B24B5/00
CPC分类号： B24B37/32 , Y10T29/49815
摘要： A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.
摘要翻译：保持环可以通过机械加工或研磨环的底部表面而在底面形成成形轮廓。保持环的底面可以包括平坦的，倾斜的和弯曲的部分。可以使用专用于研磨保持环底面的机器进行研磨。在研磨期间，可以允许环围绕环的轴线自由旋转。保持环的底面可以具有弯曲或平坦的部分。

108. 发明授权

US07315082B2 Semiconductor device having integrated circuit contact 失效
标题翻译：具有集成电路接触的半导体器件
公开(公告)号：US07315082B2
公开(公告)日：2008-01-01
申请号：US10443471
申请日：2003-05-22
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：公开了一种用于在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

109. 发明授权

US07247944B2 Connector assembly 失效
标题翻译：连接器组件
公开(公告)号：US07247944B2
公开(公告)日：2007-07-24
申请号：US11109133
申请日：2005-04-05
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L23/48 , H01L23/52 , H01L23/495 , H01L23/522
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/522 , H01L23/525 , H01L24/05 , H01L24/48 , H01L24/72 , H01L2224/02379 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4826 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099 , H01L2924/00012 , H01L2224/05552
摘要： An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternatively, a connector may contact a portion of the conductive trace to make contact therewith.
摘要翻译：一种用于将半导体管芯附接到引线框架的装置和方法，其中半导体管芯的电接触点通过多个导电迹线重新定位到半导体管芯的外围。多个引线从引线框架延伸出靠近半导体管芯外围的导电迹线，并且以LOC布置直接附接到导电迹线并与之形成电接触。或者，连接器可以接触导电迹线的一部分以与其接触。

110. 发明授权

US07202104B2 Co-sputter deposition of metal-doped chalcogenides 有权
公开(公告)号：US07202104B2
公开(公告)日：2007-04-10
申请号：US10878060
申请日：2004-06-29
申请人： Jiutao Li , Allen McTeer , Gregory Herdt , Trung T. Doan
发明人： Jiutao Li , Allen McTeer , Gregory Herdt , Trung T. Doan
IPC分类号： H01L21/00
CPC分类号： C23C14/548 , C23C14/0623 , C23C14/3464 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/1625
摘要： The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

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