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101. 发明申请

US20110230001A1 MULTIBIT ELECTRO-MECHANICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：多电子机电存储器件及其制造方法
公开(公告)号：US20110230001A1
公开(公告)日：2011-09-22
申请号：US13116374
申请日：2011-05-26
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
IPC分类号： H01L21/00
CPC分类号： H01L27/10 , G11C11/50 , H01L27/115
摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.
摘要翻译：多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线网站。

102. 发明申请

US20110189829A1 METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES 审中-公开
标题翻译：制作具有堆叠结构的非易失性存储器件的方法
公开(公告)号：US20110189829A1
公开(公告)日：2011-08-04
申请号：US13084778
申请日：2011-04-12
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/78648 , H01L29/78696 , H01L29/7926
摘要： A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.
摘要翻译：存储器件包括衬底上的第一有源区和衬底上的第一和第二源极/漏极区，邻接第一有源区的相应的第一和第二侧壁。第一栅极结构设置在第一和第二源/漏区之间的第一有源区上。第二有源区域设置在第一栅极结构之间并邻接第一和第二源极/漏极区域。第二栅极结构设置在覆盖第一栅极结构的第二有源区上。

103. 发明授权

US07973343B2 Multibit electro-mechanical memory device having cantilever electrodes 失效
标题翻译：具有悬臂电极的多位机电记忆装置
公开(公告)号：US07973343B2
公开(公告)日：2011-07-05
申请号：US12154473
申请日：2008-05-23
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
IPC分类号： H01L29/66 , H01L29/84 , H01L21/00
CPC分类号： H01L27/10 , G11C11/50 , H01L27/115
摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.
摘要翻译：多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线网站。

104. 发明申请

US20110124194A1 METHODS OF MANUFACTURING SEMICONDUCTORS USING DUMMY PATTERNS 有权
标题翻译：使用DUMMY PATTERNS制造半导体的方法
公开(公告)号：US20110124194A1
公开(公告)日：2011-05-26
申请号：US12953686
申请日：2010-11-24
申请人： Byoung-Ho KWON , Bo-Un YOON , Min-Sang KIM
发明人： Byoung-Ho KWON , Bo-Un YOON , Min-Sang KIM
IPC分类号： H01L21/302 , H01L21/306
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31053 , H01L21/76819 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.
摘要翻译：提供一种制造半导体器件的方法。在限定为包括主图案区域和虚设图案区域的基板上形成图案层。可以通过图案化图案层来形成预备主图案和初步虚拟图案，使得预备虚拟图案的背离基板表面的上表面区域小于虚设图案区域的整个区域进行随后的平面化。部分蚀刻初步主图案和初步虚拟图案以形成主图案和虚拟图案。

105. 发明授权

US07935600B2 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method 有权
标题翻译：使用该方法制造多通道晶体管器件和多通道晶体管器件的方法
公开(公告)号：US07935600B2
公开(公告)日：2011-05-03
申请号：US12637114
申请日：2009-12-14
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性蚀刻以限定在有源扩展区域中的第一通道条，该有源扩展区域在有源区域的第一和第二横向分离部分之间延伸，而第二通道条是有源区的未蚀刻部分。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

106. 发明授权

US07911011B2 Methods of fabricating electromechanical non-volatile memory devices 失效
标题翻译：制造机电非易失性存储器件的方法
公开(公告)号：US07911011B2
公开(公告)日：2011-03-22
申请号：US12693783
申请日：2010-01-26
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
IPC分类号： H01L29/84
CPC分类号： H01L27/10 , G11C23/00
摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.
摘要翻译：提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。第一电极图案设置在半导体衬底上。第一电极图案暴露半导体衬底的表面的部分通过其中。在第一电极图案和半导体衬底的暴露表面上提供保形位线。位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。绝缘层图案设置在位于半导体衬底上的位线的上表面上。第二电极图案与位线间隔开并设置在绝缘层图案上。第二电极图案面向第一电极图案。还提供了相关方法。

107. 发明授权

US07871875B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07871875B2
公开(公告)日：2011-01-18
申请号：US12662083
申请日：2010-03-30
申请人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
发明人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7856 , H01L29/4925 , H01L29/4958 , H01L29/66795
摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.
摘要翻译：提供FinFET及其制造方法。 FinFET可以包括至少一个有源鳍片，至少一个栅极绝缘层图案，第一电极图案，第二电极图案和至少一对源极/漏极扩展区域。所述至少一个活性翅片可以形成在基底上。至少一个栅极绝缘层图案可以形成在至少一个活性鳍上。第一电极图案可以形成在至少一个栅极绝缘层图案上。此外，第一电极图案可以与至少一个活性鳍相交。第二电极图案可以形成在第一电极图案上。此外，第二电极图案可以具有大于第一电极图案的宽度的宽度。至少一对源极/漏极扩展区域可以形成在第一电极图案的两侧上的至少一个有源鳍片的表面上。因此，FinFET可能具有改进的容量和减小的GIDL电流。

108. 发明申请

US20110006353A1 DRAM DEVICES 审中-公开
标题翻译： DRAM设备
公开(公告)号：US20110006353A1
公开(公告)日：2011-01-13
申请号：US12830788
申请日：2010-07-06
申请人： Min-Sang KIM , Dong-Won Kim , Jun Seo , Keun-Hwi Cho , Hyun-Jun Bae , Ji-Myoung Lee
发明人： Min-Sang KIM , Dong-Won Kim , Jun Seo , Keun-Hwi Cho , Hyun-Jun Bae , Ji-Myoung Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L28/60
摘要： A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the plug, and at least one word line under the conductive plate and spaced apart from the conductive plate. The DRAM device further includes at least one first conductive pad under the conductive plate, the at least one first conductive pad being spaced apart from the conductive plate in a first state and being electrically connected to the conductive plate in a second state, the at least one first conductive pad being disposed between the plug and an adjacent word line of the at least one word line, and the at least one first conductive pad being electrically connected to a respective capacitor of the at least one capacitor.
摘要翻译： DRAM装置包括在基板上的插头，电连接到插头并与衬底重叠的导电板，基板上的至少一个电容器和与插头间隔开的至少一个电容器，以及导电板下面的至少一个字线并间隔开从导电板。 DRAM器件还包括在导电板下方的至少一个第一导电焊盘，所述至少一个第一导电焊盘在第一状态下与导电板间隔开并且在第二状态下电连接到导电板，至少一个第一导电焊盘设置在所述插头和所述至少一个字线的相邻字线之间，并且所述至少一个第一导电焊盘电连接到所述至少一个电容器的相应电容器。

109. 发明授权

US07790494B2 Method of fabricating a multi-bit electro-mechanical memory device 有权
标题翻译：制造多位机电存储器件的方法
公开(公告)号：US07790494B2
公开(公告)日：2010-09-07
申请号：US12007819
申请日：2008-01-16
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
IPC分类号： H01L21/00 , H01L35/24 , H01L51/00 , H01L29/792
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L29/0665 , H01L29/0673
摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.
摘要翻译：存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。位线可以在第一方向上形成在基板上。第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

110. 发明授权

US07719068B2 Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US07719068B2
公开(公告)日：2010-05-18
申请号：US12002668
申请日：2007-12-18
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
IPC分类号： G11C11/50
CPC分类号： H01L29/788 , G11C11/56 , G11C23/00
摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.
摘要翻译：提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触字线，并且在第二状态下与字线间隔开。

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