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1. 发明授权

US07790494B2 Method of fabricating a multi-bit electro-mechanical memory device 有权
标题翻译：制造多位机电存储器件的方法
公开(公告)号：US07790494B2
公开(公告)日：2010-09-07
申请号：US12007819
申请日：2008-01-16
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
IPC分类号： H01L21/00 , H01L35/24 , H01L51/00 , H01L29/792
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L29/0665 , H01L29/0673
摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.
摘要翻译：存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。位线可以在第一方向上形成在基板上。第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

2. 发明授权

US07719068B2 Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US07719068B2
公开(公告)日：2010-05-18
申请号：US12002668
申请日：2007-12-18
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
IPC分类号： G11C11/50
CPC分类号： H01L29/788 , G11C11/56 , G11C23/00
摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.
摘要翻译：提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触字线，并且在第二状态下与字线间隔开。

3. 发明申请

US20080185668A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080185668A1
公开(公告)日：2008-08-07
申请号：US12007819
申请日：2008-01-16
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
IPC分类号： H01L29/84 , H01L21/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L29/0665 , H01L29/0673
摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.
摘要翻译：存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。位线可以在第一方向上形成在基板上。第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

4. 发明申请

US20080144364A1 Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US20080144364A1
公开(公告)日：2008-06-19
申请号：US12002668
申请日：2007-12-18
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Eun-Jung Yun , Dong-Gun Park
IPC分类号： G11C11/50 , H01L21/00
CPC分类号： H01L29/788 , G11C11/56 , G11C23/00
摘要： There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.
摘要翻译：提供了能够增强或最大化存储器件的集成度的多位机电存储器件以及制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线，并且在第一个方向位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触字线，并且在第二状态下与字线间隔开。

5. 发明申请

US20080094895A1 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080094895A1
公开(公告)日：2008-04-24
申请号：US11803425
申请日：2007-05-15
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
IPC分类号： G11C11/34 , H01L21/44
CPC分类号： H01L27/101 , H01L27/24
摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.
摘要翻译：非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

6. 发明授权

US07511998B2 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07511998B2
公开(公告)日：2009-03-31
申请号：US11803425
申请日：2007-05-15
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
IPC分类号： G11C16/04
CPC分类号： H01L27/101 , H01L27/24
摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.
摘要翻译：非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

7. 发明申请

US20100221876A1 FIELD EFFECT TRANSISTORS WITH VERTICALLY ORIENTED GATE ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有垂直方向栅极电极的场效应晶体管及其制造方法
公开(公告)号：US20100221876A1
公开(公告)日：2010-09-02
申请号：US12754128
申请日：2010-04-05
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L21/8234 , H01L21/86
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

8. 发明授权

US08168492B2 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 有权
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US08168492B2
公开(公告)日：2012-05-01
申请号：US12754128
申请日：2010-04-05
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L21/8238
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

9. 发明申请

US20060192249A1 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 审中-公开
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US20060192249A1
公开(公告)日：2006-08-31
申请号：US11396488
申请日：2006-04-03
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

10. 发明授权

US07332386B2 Methods of fabricating fin field transistors 有权
标题翻译：散射场晶体管的制造方法
公开(公告)号：US07332386B2
公开(公告)日：2008-02-19
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

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