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1. 发明授权

US07897463B2 Methods of fabricating vertical twin-channel transistors 失效
标题翻译：制造垂直双通道晶体管的方法
公开(公告)号：US07897463B2
公开(公告)日：2011-03-01
申请号：US12651688
申请日：2010-01-04
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

2. 发明申请

US20080087941A1 Nonvolatile Memory Devices Having Stacked Structures and Methods of Fabricating the Same 有权
标题翻译：具有堆叠结构的非易失性存储器件及其制造方法
公开(公告)号：US20080087941A1
公开(公告)日：2008-04-17
申请号：US11668115
申请日：2007-01-29
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/78648 , H01L29/78696 , H01L29/7926
摘要： A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.
摘要翻译：存储器件包括衬底上的第一有源区和衬底上的第一和第二源极/漏极区，邻接第一有源区的相应的第一和第二侧壁。第一栅极结构设置在第一和第二源/漏区之间的第一有源区上。第二有源区域设置在第一栅极结构之间并邻接第一和第二源极/漏极区域。第二栅极结构设置在覆盖第一栅极结构的第二有源区上。

3. 发明申请

US20080081442A1 Methods of forming a pattern and methods of manufacturing a memory device using the same 有权
标题翻译：形成图案的方法和使用该图案的存储器件的制造方法
公开(公告)号：US20080081442A1
公开(公告)日：2008-04-03
申请号：US11605266
申请日：2006-11-29
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/02381 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/28282 , H01L27/11568 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： In a method of forming a pattern, a sacrificial layer pattern and a stop layer pattern for preventing or reducing an epitaxial growth may be formed on a substrate. The sacrificial layer pattern may have a first hole therethrough, and the first hole partially exposes a top surface of the substrate. At least one active pattern may be formed on a bottom and a sidewall of the first hole by performing a selective epitaxial growth process on the top surface of the substrate and a sidewall of the sacrificial layer pattern. The sacrificial layer pattern and the stop layer pattern for preventing or reducing the epitaxial growth may be removed from the substrate. The at least one active pattern formed by the above method may have a finer size and an improved shaped compared to a conventional active pattern formed by directly patterning layers using a photoresist pattern. Damages in a photolithography process may be prevented or reduced from being generated.
摘要翻译：在形成图案的方法中，可以在基板上形成用于防止或减少外延生长的牺牲层图案和停止层图案。牺牲层图案可以具有穿过其的第一孔，并且第一孔部分地暴露衬底的顶表面。通过在衬底的顶表面和牺牲层图案的侧壁上执行选择性外延生长工艺，可以在第一孔的底部和侧壁上形成至少一个活性图案。可以从衬底去除用于防止或减少外延生长的牺牲层图案和停止层图案。与通过使用光致抗蚀剂图案直接图案化图案形成的常规有源图案相比，通过上述方法形成的至少一个有源图案可以具有更细的尺寸和改进的形状。可以防止或减少光刻工艺中的损伤。

4. 发明申请

US20100129976A1 Methods of Fabricating Electromechanical Non-Volatile Memory Devices 失效
标题翻译：制造机电非易失性存储器件的方法
公开(公告)号：US20100129976A1
公开(公告)日：2010-05-27
申请号：US12693783
申请日：2010-01-26
申请人： Eun Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
发明人： Eun Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
IPC分类号： H01L21/02
CPC分类号： H01L27/10 , G11C23/00
摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.
摘要翻译：提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。第一电极图案设置在半导体衬底上。第一电极图案暴露半导体衬底的表面的部分通过其中。在第一电极图案和半导体衬底的暴露表面上提供保形位线。位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。绝缘层图案设置在位于半导体衬底上的位线的上表面上。第二电极图案与位线间隔开并设置在绝缘层图案上。第二电极图案面向第一电极图案。还提供了相关方法。

5. 发明申请

US20100105181A1 METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS 失效
标题翻译：制作垂直双通道晶体管的方法
公开(公告)号：US20100105181A1
公开(公告)日：2010-04-29
申请号：US12651688
申请日：2010-01-04
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

6. 发明申请

US20080099849A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A MULTI-CHANNEL TYPE MOS TRANSISTOR 有权
标题翻译：制造具有多通道型MOS晶体管的半导体器件的制造方法
公开(公告)号：US20080099849A1
公开(公告)日：2008-05-01
申请号：US11876613
申请日：2007-10-22
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.
摘要翻译：在制造半导体器件的方法中，在衬底上形成有源沟道图案。有源沟道图案包括彼此交替堆叠的初步栅极图案和单晶硅图案。源极/漏极层形成在有源沟道图案的侧壁上。在有源沟道图案和源极/漏极层上形成包括栅极沟槽的掩模图案结构。选择性地蚀刻图案以形成隧道。然后用栅电极填充栅极沟槽。栅电极围绕有源沟道图案。栅电极从有源沟道图案突出。然后去除掩模图案结构。将杂质注入源/漏区以形成源/漏区。在源极/漏极区域上进行硅化处理以形成金属硅化物层，从而完成具有MOS晶体管的半导体器件。

7. 发明申请

US20080029811A1 Vertical Twin-Channel Transistors and Methods of Fabricating the Same 审中-公开
标题翻译：垂直双通道晶体管及其制造方法
公开(公告)号：US20080029811A1
公开(公告)日：2008-02-07
申请号：US11687079
申请日：2007-03-16
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

8. 发明授权

US08222067B2 Method of manufacturing multibit electro-mechanical memory device having movable electrode 失效
标题翻译：具有可动电极的多位机电存储器件的制造方法
公开(公告)号：US08222067B2
公开(公告)日：2012-07-17
申请号：US13116374
申请日：2011-05-26
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
IPC分类号： H01L21/00 , H01L29/66 , H01L29/84
CPC分类号： H01L27/10 , G11C11/50 , H01L27/115
摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.
摘要翻译：多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线网站。

9. 发明授权

US07943998B2 Nonvolatile memory devices having stacked structures and methods of fabricating the same 有权
标题翻译：具有堆叠结构的非易失性存储器件及其制造方法
公开(公告)号：US07943998B2
公开(公告)日：2011-05-17
申请号：US11668115
申请日：2007-01-29
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/66 , H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/78648 , H01L29/78696 , H01L29/7926
摘要： A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.
摘要翻译：存储器件包括衬底上的第一有源区和衬底上的第一和第二源极/漏极区，邻接第一有源区的相应的第一和第二侧壁。第一栅极结构设置在第一和第二源/漏区之间的第一有源区上。第二有源区域设置在第一栅极结构之间并邻接第一和第二源极/漏极区域。第二栅极结构设置在覆盖第一栅极结构的第二有源区上。

10. 发明申请

US20100155827A1 Semiconductor device having a multi-channel type MOS transistor 有权
标题翻译：具有多沟道型MOS晶体管的半导体器件
公开(公告)号：US20100155827A1
公开(公告)日：2010-06-24
申请号：US12659008
申请日：2010-02-23
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L29/78
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.
摘要翻译：在制造半导体器件的方法中，在衬底上形成有源沟道图案。有源沟道图案包括彼此交替堆叠的初步栅极图案和单晶硅图案。源极/漏极层形成在有源沟道图案的侧壁上。在有源沟道图案和源极/漏极层上形成包括栅极沟槽的掩模图案结构。选择性地蚀刻图案以形成隧道。然后用栅电极填充栅极沟槽。栅电极围绕有源沟道图案。栅电极从有源沟道图案突出。然后去除掩模图案结构。将杂质注入源/漏区以形成源/漏区。在源极/漏极区域上进行硅化处理以形成金属硅化物层，从而完成具有MOS晶体管的半导体器件。

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