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    • 93. 发明授权
    • Method for incorporating nitrogen into a dielectric layer using a special precursor
    • 使用特殊前体将氮掺入电介质层的方法
    • US06524967B1
    • 2003-02-25
    • US09630083
    • 2000-08-01
    • Prasad V. Alluri
    • Prasad V. Alluri
    • H01L21469
    • C23C16/308C07F5/003C07F7/003C07F9/005H01L21/28568H01L21/31691
    • A metal-organic precursor suitable for use in a chemical vapor deposition formation of dielectric layer is disclosed. The precursor comprises a moiety that includes a first metal atom, an oxygen atom, and a nitrogen atom. The oxygen atom is chemically bonded to the metal atom and to the nitrogen atom. The first metal atom may be a Group III, Group IV, or Group V transition metals such as yttrium, lanthanum, titanium, zirconium, hafnium, niobium, and tantalum or another metal such as aluminum. The precursor may include one or more alkoxy groups bonded to the first metal atom. The precursor may be characterized as a M(OCR3)X−Y−Z(ONR2)Y(OSiR3)Z molecule where Y is an integer from 1 to (X−1), Z is an integer from 0 to X−1, X is an integer from 3 to 5 depending upon the valency of M and (Y+Z) is less than or equal to X. In one embodiment the precursor further includes one or more siloxy or alkyl siloxy groups bonded to the first metal atom. The precursor is suitable for chemical vapor deposition process used to deposit a dielectric layer on a semiconductor substrate. In this embodiment, the dielectric layer may be intended as a gate dielectric layer or a capacitor dielectric layer.
    • 公开了一种适用于介电层化学气相沉积形成的金属有机前驱体。 前体包括包含第一金属原子,氧原子和氮原子的部分。 氧原子与金属原子和氮原子化学键合。 第一金属原子可以是III族,IV族或V族过渡金属如钇,镧,钛,锆,铪,铌和钽,或另一种金属如铝。 前体可以包括键合到第一金属原子上的一个或多个烷氧基。 前体可以表征为M(OCR3)XYZ(ONR2)Y(OSiR3)Z分子,其中Y是从1到(X-1)的整数,Z是从0到X-1的整数,X是整数 根据M和(Y + Z)的化合价,3至5是小于或等于X.在一个实施方案中,前体还包括键合到第一金属原子上的一个或多个甲硅烷氧基或烷基甲硅烷氧基。 前体适用于在半导体衬底上沉积介电层的化学气相沉积工艺。 在该实施例中,电介质层可以用作栅极介电层或电容器介电层。
    • 94. 发明授权
    • Reduction of shrinkage of poly(arylene ether) for low-K IMD
    • 降低聚(亚芳基醚)对于低K IMD的收缩率
    • US06495478B1
    • 2002-12-17
    • US09336801
    • 1999-06-21
    • Syun-Ming Jang
    • Syun-Ming Jang
    • H01L21469
    • H01L21/02118H01L21/02282H01L21/31144H01L21/312H01L21/76801H01L21/7681H01L21/76828
    • A method for forming upon a substrate employed within a microelectronics fabrication a dielectric layer. There is provided a substrate upon which is formed a patterned microelectronics layer. There is then formed upon and over the substrate at least one low dielectric constant dielectric layer formed employing a spin-on-polymer (SOP) low dielectric constant dielectric material. There is then cured the low dielectric constant dielectric layer at an elevated temperature. There is then subsequently annealed the low dielectric constant dielectric layer at a temperature selected to be lower than the curing temperature For a selected time interval so as to attenuate shrinkage and stabilize physical and chemical properties of the dielectric layer
    • 一种用于在微电子制造中使用的衬底上形成介电层的方法。 提供了一个基板,在其上形成图案化的微电子层。 然后在衬底上形成至少一个使用旋涂聚合物(SOP)低介电常数介电材料形成的低介电常数介电层。 然后在升高的温度下固化低介电常数介电层。 然后在选择低于固化温度的温度下对低介电常数电介质层进行退火。对于所选择的时间间隔,以减小收缩并稳定介电层的物理和化学性质
    • 97. 发明授权
    • Method for preventing polysilicon stringer in memory device
    • 防止存储器件中多晶硅桁条的方法
    • US06455440B1
    • 2002-09-24
    • US09903668
    • 2001-07-13
    • Pei-Ren Jeng
    • Pei-Ren Jeng
    • H01L21469
    • H01L21/28273H01L29/42324Y10S438/911
    • In accordance with the present invention, a method for preventing polysilicon stringers in memory devices is disclosed. The key aspect of the present invention is the formation of a floating gate structure with multi-level oxidation rates the lower portion of the floating gate structure the higher oxidation rate, such as a floating gate structure with two polysilicon layers of different doping concentration or crystallinity the lower polysilicon layer the higher doping concentration, or the lower polysilicon layer the higher crystallinity. Therefore, in a later oxidation process a desired profile of the floating gate structure for etch process defining word lines is formed, that is from lower portion to higher portion of the floating gate structure an increasing width profile is formed. The width of the upper portion of the floating gate structure is bigger than that of the lower portion of the floating gate structure. Thus, the anisotropic etching process of isolating the word lines maintains an ideal etching result, in other words, the polysilicon stringers in the etched region which short out the word lines is eliminated.
    • 根据本发明,公开了一种用于防止存储器件中多晶硅桁条的方法。 本发明的关键方面是形成具有多电平氧化速率的浮栅结构,浮栅结构的下部具有较高的氧化速率,例如具有不同掺杂浓度或结晶度的两个多晶硅层的浮栅结构 较低的多晶硅层掺杂浓度较高,或较低的多晶硅层具有较高的结晶度。 因此,在稍后的氧化过程中,形成用于定义字线的蚀刻工艺的浮动栅极结构的所需轮廓,即从浮动栅极结构的下部到较高部分形成增加的宽度分布。 浮动栅极结构的上部的宽度大于浮动栅极结构的下部的宽度。 因此,隔离字线的各向异性蚀刻处理保持理想的蚀刻结果,换句话说,消除了字线短路的蚀刻区域中的多晶硅桁条。
    • 99. 发明授权
    • Precleaning process for metal plug that minimizes damage to low-&kgr; dielectric
    • 金属插塞的预清洗工艺可最大限度地降低对低kappa电介质的损伤
    • US06346489B1
    • 2002-02-12
    • US09388991
    • 1999-09-02
    • Barney M. CohenSuraj RengarajanKenny King-Tai Ngan
    • Barney M. CohenSuraj RengarajanKenny King-Tai Ngan
    • H01L21469
    • H01L21/02063H01L21/3105H01L21/76814
    • The invention is a precleaning process suitable for fabricating metal plugs in a low-&kgr;, carbon-containing dielectric. More specifically, the invention is a process for cleaning a contact area of a metal conductor on a semiconductor workpiece so as to minimize damage to a low-&kgr;, carbon-containing dielectric overlying the metal. After forming contact openings in the low-&kgr; dielectric so as to expose contact areas on the underlying metal conductor, the contact areas are cleaned by exposing the workpiece to an atmosphere formed by plasma decomposition of a mixture of hydrogen-containing and helium gases. Surprisingly, our preclean process can repair damage to the dielectric caused by preceding process steps, such as oxygen plasma ashing processes for removing photoresist.
    • 本发明是适用于制造低κ,含碳电介质中的金属塞的预清洗方法。 更具体地,本发明是一种用于清洁半导体工件上的金属导体的接触面积的方法,以便使对覆盖金属的低κ,含碳电介质的损伤最小化。 在低k电介质中形成接触开口以暴露下面的金属导体上的接触区域之后,通过将工件暴露于由含氢和氦气的混合物的等离子体分解形成的气氛中来清洁接触区域。 令人惊讶的是,我们的预清洗工艺可以修复由先前的工艺步骤引起的介电损坏,例如用于除去光致抗蚀剂的氧等离子体灰化处理。