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    • 94. 发明申请
    • SEMICONDUCTOR PACKAGE
    • 半导体封装
    • WO2017186627A1
    • 2017-11-02
    • PCT/EP2017/059627
    • 2017-04-24
    • TECHNISCHE HOCHSCHULE INGOLSTADT
    • ELGER, GordonPFORR, Johannes
    • H01L25/07
    • H01L23/3675H01L21/50H01L23/10H01L23/147H01L23/315H01L23/3735H01L23/5385H01L23/5389H01L24/32H01L25/071H01L2224/32157H01L2224/8384H01L2924/1203H01L2924/1301H01L2924/13033H01L2924/13055H01L2924/13091H01L2924/14252H01L2924/19051H01L2924/19105H02P27/08
    • FDST Patentanwälte, Nürnberg Seite A semiconductor package (1, 1', 1''), the package (1, 1', 1'') comprising a first substrate (2) comprising at a front cavity side (5') a plurality of cavities (6, 6'), each of the cavities (6, 6') having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6'), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6') at the front cavity side (5') of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6') are electrically conductive bonded in a material-locking manner, and a second substrate (3), the seond substrate (3) being attached with a connection side (12, 13) to the front cavity side (5') of the first substrate (2) thereby encapsulating the semiconductor elements (16, 17) located within the corresponding cavities (6, 6') at the front cavity side (5') of the first substrate (2).
    • 一种半导体封装(1,1',1“),该封装(1,1',1”)包括第一基板(2)和第二基板 包括在前腔侧(5')处的多个空腔(6,6'),每个空腔(6,6')具有底壁(7)和侧壁(8),并且具有导电路径 (10)形成位于空腔(6,6')的底壁(7)的内侧的电接触表面(9),多个半导体元件(16,7),每个半导体元件 包括在第一侧(26)上的第一电接触表面(9)和在与第一侧(26)相对的第二侧(28)上的第二电接触表面(9),其中至少一个 所述半导体元件(16,17)被放置在所述第一基板(2)的所述前腔侧(5')处的相应空腔(6,6')内,其中所述半导体元件(16,17)的所述第一电触点(27) 内部si处的电接触表面(9) (6,6')的底壁(7)的第一基板(3)以材料锁定的方式导电结合;以及第二基板(3),所述第二基板(3)以连接侧 (2')的前腔侧(5'),从而将位于相应腔(6,6')内的半导体元件(16,17)封装在前腔侧(5')处, 的第一衬底(2)。
    • 96. 发明申请
    • INTERCONNECT PATTERN FOR TRANSCEIVER PACKAGE
    • 收发器包装的互连模式
    • WO2011100207A3
    • 2011-11-17
    • PCT/US2011023964
    • 2011-02-08
    • ALTERA CORPJIANG XIAOHONGSHI HONG
    • JIANG XIAOHONGSHI HONG
    • H01L23/48H01L21/60H01L23/535
    • H01L23/66H01L23/50H01L23/5286H01L2223/6638H01L2924/0002H01L2924/19051H01L2924/3011H01L2924/00
    • In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package. In the first row, ground contacts alternate with contacts for receiving differential signals and in the second row ground contacts alternate with contacts for transmitting differential signals. The third row of contacts is located between the first and second rows and contains contacts for receiving differential signals that alternate with contacts for transmitting differential signals. The ground contacts in the second row are offset by one column from the ground contacts in the first row. In a second embodiment, the receiving contacts in the third row are in the same column as the receiving contacts in the first row; and the transmitting contacts in the third row are in the same column as the transmitting contacts in the second row. In a third embodiment, the contacts in the third row are offset by one column from the corresponding contacts in the first or second rows. Each pair of contacts for receiving differential signals is formed by a contact in the first row and an adjacent contact in the third row; and each pair of contacts for transmitting differential signals is formed by a contact in the second row and an adjacent contact in the third row.
    • 在一个实施例中,信令和接地触点位于沿着诸如BGA封装的互连封装的至少一个边缘的至少两个平行直线排中。 在一行中,多个接地触点中的每一个位于用于接收差分信号的两对触点之间。 在第二行中,多个接地触点中的每一个位于用于传输差分信号的两对触点之间,并且第二行中的接地触点与第一行中的接地触点偏移一列。 结果,信令对与接地触点的比例为2:2。 还可以使用另外的行对。 在其他实施例中,信号和接地触点沿着包装的至少一个边缘位于三个平行的直线行中。 在第一行中,接地触点与用于接收差分信号的触点交替,而在第二行中,接地触点与用于传输差分信号的触点交替。 第三行触点位于第一行和第二行之间,并且包含用于接收与用于传输差分信号的触点交替的差分信号的触点。 第二行的接地触点与第一行的接地触点偏移一列。 在第二实施例中,第三行中的接收触点与第一行中的接收触点在同一列中; 并且第三行中的发送触点与第二行中的发送触点在同一列中。 在第三实施例中,第三行中的触点从第一行或第二行中的对应触点偏移一列。 用于接收差分信号的每对触点由第一行中的触点和第三行中的相邻触点形成; 并且用于传输差分信号的每对触点由第二行中的触点和第三行中的相邻触点形成。
    • 97. 发明申请
    • ENHANCED SUBSTRATE USING METAMATERIALS
    • 使用金属材料的增强基材
    • WO2007069224A3
    • 2007-11-15
    • PCT/IB2006054899
    • 2006-12-15
    • NXP BVWYLAND CHRIS
    • WYLAND CHRIS
    • H01L23/66H01P3/08H01Q15/00H05K1/02
    • H01Q15/0086H01L23/64H01L2924/0002H01L2924/19051H01L2924/3011H05K1/0236H01L2924/00
    • In enhancing signal quality through packages, meta-materials may be used. Meta-materials are designed to make the signal act in such a way as to make the shape of the signal behave as though the permittivity and permeability are different than the real permittivity and permeability of the insulator used. In an example embodiment, a substrate (10) is configured as a meta-material. The meta-material provides noise protection for a signal line (15) having a pre-determined length disposed on the meta-material. The substrate comprises a dielectric material (2, 4, 6) having a topside surface and an underside surface. A conductive material (30) is arranged into pre-determined shapes (35) having a collective length. Dielectric material envelops the conductive material and the conductive material is disposed at a first predetermined distance (55) from the topside surface and at a second predetermined distance from the underside surface. The collective length of the conductive material (30) is comparable to the pre-determined length of the signal line (15).
    • 通过包装提高信号质量,可以使用超材料。 元材料被设计成使信号的作用方式使得信号的形状表现得如同介电常数和磁导率不同于使用的绝缘体的实际介电常数和磁导率。 在示例性实施例中,衬底(10)被配置为超常材料。 超临界材料为具有设置在超常材料上的预定长度的信号线(15)提供噪声保护。 衬底包括具有顶侧表面和下表面的电介质材料(2,4,6)。 导电材料(30)被布置成具有共同长度的预定形状(35)。 电介质材料包围导电材料,并且导电材料设置在与顶侧表面相距第一预定距离(55)处并且距离下表面第二预定距离。 导电材料(30)的总长度与信号线(15)的预定长度相当。