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91. 发明专利

JP2007067376A System and method for photolithography in semiconductor manufacture 审中-公开
标题翻译：半导体制造中的光刻技术的系统和方法
公开(公告)号：JP2007067376A
公开(公告)日：2007-03-15
申请号：JP2006183322
申请日：2006-07-03
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾積體電路製造股▲ふん▼有限公司
发明人： CHEN KUEI SHUN , LIN CHIN-HSIANG , LU DING CHUNG
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： G03F7/70341 , G03F7/203 , G03F7/70466
摘要： PROBLEM TO BE SOLVED: To provide a system for photolithography in semiconductor manufacture combining an advantage of high accuracy which high accuracy exposure has and an advantage of low cost which low accuracy exposure has, and to provide a method for it. SOLUTION: In a step 14, a wafer is prepared. In a step 16, at least one exposure is performed for the wafer by liquid immersion lithography. Further in a step 18, at least one exposure is performed for the wafer by dry lithography. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体制造中的光刻系统，其结合具有高精度曝光的高精度优点和低精度曝光具有的低成本优点，并提供其方法。解决方案：在步骤14中，制备晶片。在步骤16中，通过液浸光刻对晶片进行至少一次曝光。此外，在步骤18中，通过干式光刻对晶片进行至少一次曝光。版权所有（C）2007，JPO＆INPIT

92. 发明专利

JP2007047782A Method of immersion lithography process on semiconductor substrate and method for treating semiconductor wafer 有权
标题翻译：半导体衬底上的倾斜光刻工艺及其半导体晶体管理方法
公开(公告)号：JP2007047782A
公开(公告)日：2007-02-22
申请号：JP2006212576
申请日：2006-08-03
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾積體電路製造股▲ふん▼有限公司
发明人： CHANG CHING-YU , YU DAIKEI
IPC分类号： G03F7/38 , H01L21/027
CPC分类号： G03F7/2041 , G03F7/70341
摘要： PROBLEM TO BE SOLVED: To provide a method of immersion lithography process with reduced watermark.
SOLUTION: The method for performing immersion lithography on a semiconductor substrate includes supplying a resist layer 14 on the surface of a semiconductor substrate 10 and exposing the resist layer 14 by using an immersion lithography exposure system 20. The immersion lithography exposure system 20 utilizes a fluid 26 during exposure and may be capable of removing some, but not all, of the fluid 26 after exposure. After exposure, a treatment process is used to neutralize the effect of undesirable elements that are diffused into the resist layer 14 during immersion exposure. After the treatment, a post exposure bake and a development step are used.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有减少水印的浸没式光刻工艺的方法。解决方案：在半导体衬底上进行浸渍光刻的方法包括在半导体衬底10的表面上提供抗蚀剂层14，并通过使用浸没光刻曝光系统20曝光抗蚀剂层14.浸渍光刻曝光系统20 在曝光期间利用流体26，并且可以在曝光后能够去除一些但不是全部的流体26。曝光后，使用处理工艺来中和在浸没曝光期间扩散到抗蚀剂层14中的不期望的元件的影响。处理后，使用后曝光烘烤和显影步骤。版权所有（C）2007，JPO＆INPIT

93. 发明专利

JP2007036194A Mismatching of device performance reducing method, and semiconductor circuit 审中-公开
标题翻译：器件性能降低方法的分离和半导体电路
公开(公告)号：JP2007036194A
公开(公告)日：2007-02-08
申请号：JP2006136426
申请日：2006-05-16
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾積體電路製造股▲ふん▼有限公司
发明人： CHUNG SHINE CHIEN , RO TEICHU
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092
CPC分类号： H01L27/105 , H01L21/823481 , H01L27/0203
摘要： PROBLEM TO BE SOLVED: To provide a method and a circuit for reducing mismatching of devices that is caused by stress from groove separation.
SOLUTION: One or more expansive active regions 402 are formed on a substrate. The active region 402 is expanded from one or more ends of the substrate. One or more operation devices 408 are arranged in one or more active regions. The expansive active region 402 has a length at least twice the distance between gates of two adjoining operation devices 408.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少由槽分离的应力引起的装置不匹配的方法和电路。解决方案：在衬底上形成一个或多个膨胀的有源区402。有源区域402从衬底的一个或多个端部扩展。一个或多个操作装置408布置在一个或多个活动区域中。膨胀的有源区域402的长度至少是两个邻接的操作装置408的门之间的距离的两倍。版权所有：（C）2007，JPO＆INPIT

94. 发明专利

JP2006310862A Thermoelectric heating and cooling apparatus for processing semiconductor 审中-公开
标题翻译：用于加工半导体的热电加热和冷却装置
公开(公告)号：JP2006310862A
公开(公告)日：2006-11-09
申请号：JP2006122732
申请日：2006-04-26
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾セミコンダクターマニュファクチャリングカンパニーリミテッドTaiwan Semiconductor Manufacturing Co., Ltd.
发明人： LIN YU-LIANG , LIN CHIN-HSIEN , CHIEN-RIN FAN
IPC分类号： H01L21/02
CPC分类号： H01L35/32 , H01L21/67109 , H01L35/325
摘要： PROBLEM TO BE SOLVED: To provide a thermoelectric wafer chuck which is applied to a semiconductor process for performing rapid, dynamic and multi-zone temperature control with respect to a wafer.
SOLUTION: A thermoelectric wafer chuck 22 includes a chuck base and a wafer support surface. Fluid channels extend through the wafer base for distribution of a cooling or a heating liquid. A thermoelectric module is provided in thermal contact with the wafer support surface. The thermoelectric wafer chuck is capable of heating a wafer, based on the wafer support surface as the thermoelectric module 22 converts electrical energy into thermal energy in accordance to the Peltier effect. The wafer is cooled by a reverse flow of current through the thermoelectric module, by making a cooling medium distribute through the cooling channels, or both of these methods.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种应用于半导体工艺的热电晶片卡盘，用于对晶片执行快速，动态和多区域温度控制。解决方案：热电晶片卡盘22包括卡盘基座和晶片支撑表面。流体通道延伸穿过晶片底座以分配冷却或加热液体。提供与晶片支撑表面热接触的热电模块。热电晶片卡盘能够基于晶片支撑表面加热晶片，因为热电模块22根据珀耳帖效应将电能转换成热能。通过使冷却介质分配通过冷却通道，或者这两种方法，通过热电模块的反向流动来冷却晶片。版权所有（C）2007，JPO＆INPIT

95. 发明专利

JP2006287232A Matching type optical measurement for dynamically controlling critical dimension (cd), and lithographic process system 审中-公开
标题翻译：用于动态控制关键尺寸（CD）和光刻过程系统的匹配型光学测量
公开(公告)号：JP2006287232A
公开(公告)日：2006-10-19
申请号：JP2006101810
申请日：2006-04-03
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾積體電路製造股▲ふん▼有限公司
发明人： KE CHIH-MING , YU SHING-SHEN , WANG YU-HSI , GAU TSAI-SHENG , KO TOKUCHI
IPC分类号： H01L21/027
CPC分类号： G03F7/70625
摘要： PROBLEM TO BE SOLVED: To enhance the productivity of wafers by improving CD during photoresist process and uniformity of CD.
SOLUTION: The following steps are included. A first resist layer is formed on a first process wafer. In a heating process, a first resist pattern is formed on the first resist layer, based on a first temperature curve. After this, light beams scattered from the first resist pattern are generated and collected. Then, 3D data of the CD of the first resist pattern is obtained by processing the scattered light beams. Subsequently, the CD of a second resist pattern is obtained, by determining a second temperature curve necessary for the heating process. In the CD of the second resist pattern, the second resist pattern on a second process wafer is included. Finally, in the heating process, the second resist pattern is formed based on the second temperature curve.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过改善光致抗蚀剂工艺中的CD和CD的均匀性来提高晶片的生产率。
解决方案：包括以下步骤。在第一工艺晶片上形成第一抗蚀剂层。在加热过程中，基于第一温度曲线在第一抗蚀剂层上形成第一抗蚀剂图案。之后，产生并收集从第一抗蚀剂图案散射的光束。然后，通过处理散射光获得第一抗蚀剂图案的CD的3D数据。随后，通过确定加热过程所需的第二温度曲线，获得第二抗蚀剂图案的CD。在第二抗蚀剂图案的CD中，包括第二处理晶片上的第二抗蚀剂图案。最后，在加热过程中，基于第二温度曲线形成第二抗蚀剂图案。版权所有（C）2007，JPO＆INPIT

96. 发明专利

JP2006237575A Wafer repair method of direct-writing system 有权
标题翻译：直接写字系统的WAFER修复方法
公开(公告)号：JP2006237575A
公开(公告)日：2006-09-07
申请号：JP2006000849
申请日：2006-01-05
申请人： Taiwan Semiconductor Manufacturing Co Ltd , タイワンセミコンダクターマニュファクチャリングカンパニーリミテッド
发明人： LIN CHIN-HSIANG , LIN BURN JENG , GAU TSAI-SHENG
IPC分类号： H01L21/02 , H01L21/3205 , H01L23/52
CPC分类号： G03F7/7065 , G03F7/70383 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wafer repair method of a direct-writing system capable of decreasing a time duration and a cost by carrying out a processing by means of the direct-writing system in a repair process. SOLUTION: The wafer repair method comprises steps of: searching for plural locations and patterns in plural defective regions out of a semiconductor wafer 100; transmitting the locations and the patterns in the defective regions to a direct-writing tool 220; forming a photoresist layer on the semiconductor wafer 100; locally exposing the photoresist layer within the defective regions by using an energy beam; developing the photoresist layer on the semiconductor wafer 100; and processing the semiconductor wafer 100 under the photoresist layer after exposing and developing. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够通过在修复过程中通过直接写入系统进行处理来减少持续时间和成本的直接写入系统的晶片修复方法。解决方案：晶片修复方法包括以下步骤：从半导体晶片100中搜索多个缺陷区域中的多个位置和图案; 将缺陷区域中的位置和图案发送到直写工具220; 在半导体晶片100上形成光致抗蚀剂层; 通过使用能量束将缺陷区域内的光致抗蚀剂层局部曝光; 在半导体晶片100上显影光致抗蚀剂层; 以及在曝光和显影之后在光致抗蚀剂层下方处理半导体晶片100。版权所有（C）2006，JPO＆NCIPI

97. 发明专利

JP2006210923A System for manufacturing pattern on substrate and method therefor 有权
标题翻译：用于制造基板上的图案的系统及其方法
公开(公告)号：JP2006210923A
公开(公告)日：2006-08-10
申请号：JP2006016904
申请日：2006-01-25
申请人： Taiwan Semiconductor Manufacturing Co Ltd , タイワンセミコンダクターマニュファクチャリングカンパニーリミテッド
发明人： LIN CHIN-HSIANG , LIN BURN JENG
IPC分类号： H01L21/027 , G03F7/00 , G03F7/20
CPC分类号： G03F7/70466 , G03F7/001 , G03F7/201 , G03F7/203 , G03F7/70408
摘要： PROBLEM TO BE SOLVED: To provide an interference photolithography system for manufacturing a pattern in a photosensitive material, and to provide a method therefore. SOLUTION: The invention comprises the steps of classifying patterns into a first subpattern, comprising a plurality of lines turning in a first direction and a second subpattern, comprising a plurality of lines turning in a second direction; forming the plurality of first lines turning in the first direction on a first photosensitive material layer on a substrate by using a first standing wave interference pattern; forming the first subpattern by trimming a part of the first line; providing a second photosensitive material layer, after forming the first subpattern; forming the plurality of second lines turning in the second direction on the second photosensitive material layer by using a second standing wave interference pattern; and forming the second subpattern by trimming a part of the second line. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于制造感光材料中的图案的干涉光刻系统，并因此提供一种方法。解决方案：本发明包括将图案分类为第一子图案的步骤，包括沿第一方向转动的多条线和第二子图案，包括沿第二方向转动的多条线; 通过使用第一驻波干涉图案，在基板上的第一感光材料层上形成在第一方向上转动的多条第一线; 通过修剪第一行的一部分来形成第一子模式; 在形成第一子图案之后提供第二感光材料层; 通过使用第二驻波干涉图形形成在第二感光材料层上沿第二方向转动的多条第二线; 以及通过修剪所述第二线的一部分来形成所述第二子图案。版权所有（C）2006，JPO＆NCIPI

98. 发明专利

JP2006148133A Immersion photolithography with megasonic ultrasonic rinse 有权
标题翻译：具有MEGASONIC超声波冲击的平滑光刻技术
公开(公告)号：JP2006148133A
公开(公告)日：2006-06-08
申请号：JP2005337792
申请日：2005-11-22
申请人： Taiwan Semiconductor Manufacturing Co Ltd , タイワンセミコンダクターマニュファクチャリングカンパニーリミテッド
发明人： CHANG CHING-YU
IPC分类号： H01L21/027
CPC分类号： G03F7/2041 , G03F7/168 , H01L21/67051 , H01L21/67057
摘要： PROBLEM TO BE SOLVED: To prevent a photoresist material from being melted into an immersion exposure solution to cause contamination. SOLUTION: A method comprises steps for forming a photoresist on a substrate, rinsing the photoresist using a rinse liquid agitated by at least one megasonic ultrasonic source, exposing the photoresist to radiation while being immersed in liquid, and developing the photoresist. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止光致抗蚀剂材料熔化成浸没曝光溶液以引起污染。解决方案：一种方法包括在衬底上形成光致抗蚀剂的步骤，用至少一个兆声波超声波源搅拌的冲洗液冲洗光致抗蚀剂，在浸没在液体中时使光致抗蚀剂暴露于辐射，并显影光致抗蚀剂。版权所有（C）2006，JPO＆NCIPI

99. 发明专利

JP2006005338A Semiconductor integrated circuit structure and manufacturing method therefor 审中-公开
标题翻译：半导体集成电路结构及其制造方法
公开(公告)号：JP2006005338A
公开(公告)日：2006-01-05
申请号：JP2005145274
申请日：2005-05-18
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台灣積體電路製造股▲分▼有限公司
发明人： HUANG SHAO-CHANG , RI TAKEOKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/06
CPC分类号： H01L27/0255 , H01L27/0814 , H01L29/0619
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit structure and its manufacturing method.
SOLUTION: The semiconductor integrated circuit structure has a plurality of diodes, and at least one fit-in region and one voltage supply node. The diodes are installed in a substrate and are electrically connected in series. At least one fit-in region is set in the substrate, such that it is installed in between two diodes. The voltage supply node is electrically connected to the fit-in region. Further, preferably, these diodes are surrounded by guard rings.
COPYRIGHT: (C)2006,JPO&NCIPI

100. 发明专利

JP2005340808A Barrier structure of semiconductor device 审中-公开
标题翻译：半导体器件的阻挡结构
公开(公告)号：JP2005340808A
公开(公告)日：2005-12-08
申请号：JP2005144753
申请日：2005-05-17
申请人： Taiwan Semiconductor Manufacturing Co Ltd , 台湾積體電路製造股▲ふん▼有限公司
发明人： HAYASHI TOSHINARI , SHUE SHAU-LIN
IPC分类号： H01L21/768 , H01L21/4763 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76865
摘要： PROBLEM TO BE SOLVED: To provide a barrier structure for reducing the contact resistance of a contact or a via formed in a semiconductor device.
SOLUTION: A via 120 having a barrier layer structure is provided. In an embodiment, a via 120 is formed by forming a barrier layer. The barrier layer along the bottom of the via 120 is partially or completely removed, and the via 120 is filled with a conductive material. In another embodiment, a first barrier layer 130 is formed along the bottom and sidewalls of the via 120. Thereafter, the first barrier layer 130 along the bottom of the via 120 is partially or completely removed, and a second barrier layer 240 is formed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于降低半导体器件中形成的接触或通孔的接触电阻的阻挡结构。提供具有阻挡层结构的通孔120。在一个实施例中，通过形成阻挡层形成通孔120。沿着通孔120的底部的阻挡层被部分地或完全地去除，并且通孔120填充有导电材料。在另一个实施例中，沿着通孔120的底部和侧壁形成第一阻挡层130.此后，沿着通孔120的底部的第一阻挡层130被部分地或完全地去除，并且形成第二阻挡层240。版权所有（C）2006，JPO＆NCIPI

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