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91. 发明申请

US20080140920A1 Microcomputer for flash memory rewriting 有权
标题翻译：微机用于闪存重写
公开(公告)号：US20080140920A1
公开(公告)日：2008-06-12
申请号：US12000001
申请日：2007-12-06
申请人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
发明人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
摘要翻译：提供一种微计算机和方法，其能够在重写非易失性存储器失败时重新启动重写程序，而不需要使用外部端子改变模式。微型计算机的CPU执行重写程序来清除闪存的FLASH状态0并重写其中的所有区域。 CPU最终将重写完成代码写入FLASH状态0。 CPU执行确定程序以读取闪存的FLASH状态0。当读取数据与重写完成代码不匹配时，CPU读取ID状态信息。当数据与ID状态信息匹配时，CPU重新执行重写程序。

92. 发明授权

US06794921B2 Clamp circuit 有权
标题翻译：钳位电路
公开(公告)号：US06794921B2
公开(公告)日：2004-09-21
申请号：US10616426
申请日：2003-07-09
申请人： Hirofumi Abe , Hideaki Ishihara , Shinichi Noda
发明人： Hirofumi Abe , Hideaki Ishihara , Shinichi Noda
IPC分类号： H03K508
CPC分类号： H03K5/08
摘要： In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.
摘要翻译：在钳位电路中，第一晶体管将目标钳位电压移位栅源电压以输出目标钳位电压。缓冲电路输入移位电压，并输出输入的移位电压的参考电压。第二晶体管的栅极连接到缓冲电路的输出端。第二晶体管的源极连接到第一晶体管的输入端。在该结构中，参考电压被提供给第二晶体管的栅极，使得当IC的输入端子的端电压不小于对应于参考电压和阈值电压之和的钳位电压时第二晶体管，第二晶体管导通，由此端子电压被钳位到与目标钳位电压相关的钳位电压。

93. 发明授权

US06697938B1 Microcomputer executing an ordinary branch instruction and a special branch instruction 失效
标题翻译：微机执行普通分支指令和特殊分支指令
公开(公告)号：US06697938B1
公开(公告)日：2004-02-24
申请号：US09598320
申请日：2000-06-21
申请人： Masahiro Kamiya , Hideaki Ishihara
发明人： Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F932
CPC分类号： G06F9/30054
摘要： A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction “JM” as an executable instruction. The specific area branch instruction “JM” is a branch instruction restricted to jump to only a specific area of a memory space and is a single instruction having a minimum instruction length. The microcomputer allocates at least one of a real arithmetic subroutine, an integer division subroutine, and a bit handling subroutine to the specific area. A program of this microcomputer is configured to jump to the selected subroutine allocated to the specific area in response to the specific area branch instruction “JM”. Accordingly, the required program size can be reduced. When the programs are stored in the external memory, it becomes possible to suppress an increase of the execution time which is required for invoking each of the subroutines.
摘要翻译：微型计算机具有内置存储器，并可由外部存储器访问。微型计算机执行特定区域分支指令“JM”作为可执行指令。特定区域分支指令“JM”是限制仅跳转到存储器空间的特定区域的分支指令，并且是具有最小指令长度的单个指令。微计算机将特定区域中的至少一个实际运算子程序，整数除法子程序和位处理子程序分配给该特定区域。该微型计算机的程序被配置为响应于特定区域分支指令“JM”跳转到分配给特定区域的所选择的子程序。因此，可以减少所需的程序大小。当程序存储在外部存储器中时，可以抑制调用每个子程序所需的执行时间的增加。

94. 发明授权

US06653884B2 Input interface circuit for semiconductor integrated circuit device 失效
公开(公告)号：US06653884B2
公开(公告)日：2003-11-25
申请号：US09915390
申请日：2001-07-27
申请人： Hiroshi Fujii , Hideaki Ishihara
发明人： Hiroshi Fujii , Hideaki Ishihara
IPC分类号： H03K508
CPC分类号： H03K19/00315 , H01L2924/0002 , H01L2924/00
摘要： An input interface circuit for a semiconductor integrated circuit device is provided which includes a pair of diodes, first, second, and third PMOSFETs, and first, second, and third NMOSFETs. The diodes serve to clamp a high positive or negative voltage input at a level that is the sum of the power supply voltage and the forward voltage of the diodes or the difference between the ground potential and the forward voltage. The first and second PMOSFETs are connected in series between the power supply and an inside input terminal coupled to an internal circuit element of the semiconductor integrated circuit device. The first and second NMOSFETs are connected in series between ground and the inside input terminal. The third PMOSFET is connected in series between the outside input terminal and a gate of the first PMOSFET. The third NMOSFET is connected in series between the outside input terminal and a gate of the second NMOSFET. The voltage which is intermediate between ground potential and the voltage of the power supply is applied to a gate of each of the first NMOSFET, the second PMOSFET, the third PMOSFET, and the third NMOSFT. This structure serves to protect the circuit elements against an input of an undesirable higher positive or negative voltage to the input interface circuit.

95. 发明授权

US06581119B1 Interrupt controller and a microcomputer incorporating this controller 失效
标题翻译：中断控制器和包含该控制器的微型计算机
公开(公告)号：US06581119B1
公开(公告)日：2003-06-17
申请号：US09598321
申请日：2000-06-21
申请人： Kouichi Maeda , Hideaki Ishihara , Sinichi Noda
发明人： Kouichi Maeda , Hideaki Ishihara , Sinichi Noda
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.
摘要翻译：为了减小能够执行多个中断的微型计算机的CPU的电路规模，中断控制器包括中断屏蔽级别寄存器。 CPU临时将处理数据传输或堆栈到RAM中。处理数据包括当前在CPU中运行的中断处理的PSR（即，系统寄存器）值和PC（即，程序计数器）值。同时，CPU向中断控制器发送堆栈信号“STK”。响应于堆栈信号“STK”，中断控制器将存储在寄存器中的中断屏蔽电平临时传送到RAM中。当CPU重新启动暂停的中断处理时，CPU在CPU产生返回信号“RTN”时从RAM读取PSR值和PC值。响应于返回信号“RTN”，中断屏蔽电平从RAM返回到寄存器。

96. 发明授权

US06536615B2 Load moment indicator of crane 有权
标题翻译：起重机负载力矩指示器
公开(公告)号：US06536615B2
公开(公告)日：2003-03-25
申请号：US09816477
申请日：2001-03-26
申请人： Tadakazu Nishikino , Hideaki Ishihara , Kazuhiro Kobayashi , Yoshiki Kamon
发明人： Tadakazu Nishikino , Hideaki Ishihara , Kazuhiro Kobayashi , Yoshiki Kamon
IPC分类号： B66C2390
CPC分类号： B66C23/905
摘要： An load moment indicator, in a crane provided with hoist means of a main side and an auxiliary side, including a calculator in which a reference value if a rated load determined by the stability of a crane or the like is preset, a hoist load of the other side is converted into a load component of its own side, and the converted value is subtracted from a reference value of its own side to thereby obtain a rated load of own side, or in which a tolerant load that can be suspended by the other side is converted into a load component of its own side on the basis of a base of a reference value of the other side, and the converted value is compared with the reference value of its own side to select a lower value. Thereby, it is possible to make the most of the suspending ability of the main side and the auxiliary side and for an operator to grasp clearly a tolerance of the hoist load.
摘要翻译：一种负载力矩指示器，在具有主侧和辅助侧的起重机构的起重机中，包括计算器，其中如果由起重机等的稳定性确定的额定载荷被预先设定的参考值，则提升载荷另一侧被转换为其自身侧的负载分量，并且从其自身侧的基准值中减去转换值，从而获得自身侧的额定负载，或者其中可以暂停的容限负载基于另一侧的基准值的基准将另一侧转换为自身的负载分量，并将转换后的值与其自身侧的基准值进行比较以选择较低的值。由此，可以充分利用主侧和辅助侧的悬挂能力，并且能够使操作者清楚地掌握提升负载的公差。

97. 发明授权

US4946746A Novel metal fiber and process for producing the same 失效
标题翻译：新型金属纤维及其制造方法
公开(公告)号：US4946746A
公开(公告)日：1990-08-07
申请号：US280320
申请日：1988-12-06
申请人： Takaharu Ichiryu , Yoshiki Ono , Hideaki Ishihara
发明人： Takaharu Ichiryu , Yoshiki Ono , Hideaki Ishihara
IPC分类号： B22D11/00 , C30B15/00 , H01F1/153 , H01F1/20
CPC分类号： H01F1/20 , B22D11/005 , C30B15/00 , C30B15/007 , C30B29/52 , C30B29/60 , H01F1/15325 , H01F1/15391 , Y10T428/12431
摘要： A metal fiber having unidirectional dendritic texture which is an assembly of a group of dendrites wherein primary arms have grown at angle of within 20.degree. relative to the metal fiber axis, diameter of said fiber being not greater than 100 .mu.m. There is also disclosed a single crystalline metal fiber which is a single crystalline material throughout the entire length, diameter of said fiber being not greater than 100 .mu.m, length of said fiber being not less than 40 mm. These fibers can be produced by melt-spinning of metal.
摘要翻译：具有单向树枝状结构的金属纤维，其是一组枝状物的组合，其中初级臂相对于金属纤维轴线以20度的角度生长，所述纤维的直径不大于100μm。还公开了在整个长度上为单晶材料的单晶金属纤维，所述纤维的直径不大于100μm，所述纤维的长度不小于40mm。这些纤维可以通过熔融纺丝制成。

98. 发明授权

US08936167B2 Crane 有权
标题翻译：起重机
公开(公告)号：US08936167B2
公开(公告)日：2015-01-20
申请号：US13325388
申请日：2011-12-14
申请人： Hideaki Ishihara , Shintaro Sasai
发明人： Hideaki Ishihara , Shintaro Sasai
IPC分类号： B66C23/26 , B66C23/82 , B66C23/88 , B66C23/36
CPC分类号： B66C23/365 , B66C23/82 , B66C23/88
摘要： A crane includes a limiting device to limit a raising/lowering angle of the mast during suspending work to be equal to or less than an upper limit angle which is less than a value of the raising/lowering angle when the mast extends vertically; a release device into which a release instruction for causing the limiting device to release the limitation on the raising/lowering angle of the mast is input; and a first detection section adapted to detect that the mast support device is at an overhanging position where the mast support device pushes up and sets the mast in the work posture. The limiting device is operable whenever the first detection section does not detect that the mast support device is at the overhanging position, even if the release instruction is input into the release device, to prohibit the mast from being tilted rearward beyond the upper limit angle.
摘要翻译：起重机包括限制装置，用于限制在悬挂作业期间桅杆的升降角度等于或小于当桅杆垂直延伸时小于上升/下降角度值的上限角度; 输入用于使限制装置释放对桅杆的升降角度的限制的释放指令的释放装置; 以及第一检测部，其适于检测所述桅杆支撑装置处于所述桅杆支撑装置向上推动并将所述桅杆设置在所述作业姿势的悬垂位置。即使第一检测部分没有检测到桅杆支撑装置处于悬垂位置，即使释放指令被输入到释放装置中，限制装置也可以操作，以防止桅杆向后倾斜超过上限角度。

99. 发明授权

US08176263B2 Memory management apparatus and method for same 有权
标题翻译：内存管理装置及方法相同
公开(公告)号：US08176263B2
公开(公告)日：2012-05-08
申请号：US12076021
申请日：2008-03-13
申请人： Kenji Yamada , Hideaki Ishihara
发明人： Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
摘要： A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus.
摘要翻译：存储器管理装置使用链路列表存储器来管理数据存储器的使用区域和空闲区域。通过多个端口中的每一个使用数据存储器的使用区域被限制，并且数据存储器的使用区域被配置为总是为多个端口中的每个端口提供。以这种方式，防止了特定端口对数据存储器的垄断使用，并且在存储器管理装置的控制下，多个端口中的每一个被牢固地设置有数据存储器的使用区域。

100. 发明授权

US08046615B2 Microcomputer system with reduced power consumption 有权
标题翻译：微电脑系统功耗降低
公开(公告)号：US08046615B2
公开(公告)日：2011-10-25
申请号：US12285481
申请日：2008-10-07
申请人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
发明人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , Y02D10/122 , Y02D10/126
摘要： A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.
摘要翻译：除了具有主CPU的主微型计算机之外，还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。当主CPU向子CPU发出操作停止通知时，子CPU识别通知，停止对主微型计算机的供电，并将子时钟部分设置为间歇模式。子CPU确定在间歇模式的周期内操作状态条件满足，子CPU将副时钟部分切换为连续模式，以重新开始向主微型计算机供电。

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