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1. 发明授权

US08127183B2 Microcomputer system 有权
标题翻译：微电脑系统
公开(公告)号：US08127183B2
公开(公告)日：2012-02-28
申请号：US11819555
申请日：2007-06-28
申请人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
发明人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F11/00 , G06F13/26
CPC分类号： G06F11/0751 , G06F9/3802 , G06F11/0715
摘要： A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.
摘要翻译：微机系统包括CPU，存储器和失控检测器。 CPU包括用于输出任务信息信号的控制器。如果CPU执行当前最重要的任务，则任务信息信号被激活。最重要任务的程序存储在内存中。失控检测器包括地址寄存器和程序区检查器。地址寄存器存储程序区的开始和结束地址。程序区域检查器通过将执行地址与开始和结束地址中的每一个进行比较来确定CPU的执行地址是否在程序区域内。失控检测器在任务信息信号与程序区域检查器的确定结果之间发生冲突的情况下检测到任务失控。

2. 发明授权

US07934050B2 Microcomputer for flash memory rewriting 有权
标题翻译：微机用于闪存重写
公开(公告)号：US07934050B2
公开(公告)日：2011-04-26
申请号：US12000001
申请日：2007-12-06
申请人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
发明人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
IPC分类号： G06F13/00
CPC分类号： G06F12/0246
摘要： A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
摘要翻译：提供一种微计算机和方法，其能够在重写非易失性存储器失败时重新启动重写程序，而不需要使用外部端子改变模式。微型计算机的CPU执行重写程序来清除闪存的FLASH状态0并重写其中的所有区域。 CPU最终将重写完成代码写入FLASH状态0. CPU执行确定程序以读取闪存的FLASH状态0。当读取数据与重写完成代码不匹配时，CPU读取ID状态信息。当数据与ID状态信息匹配时，CPU重新执行重写程序。

3. 发明申请

US20060161763A1 Microcomputer and encoding system for instruction code and CPU 有权
标题翻译：微机和编码系统的指令代码和CPU
公开(公告)号：US20060161763A1
公开(公告)日：2006-07-20
申请号：US11330237
申请日：2006-01-12
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

4. 发明授权

US07162622B2 Microcomputer for apparatus control and vehicle-mounted electronic control unit incorporating microcomputer 有权
标题翻译：微机用于装置控制和车载电子控制单元结合微型计算机
公开(公告)号：US07162622B2
公开(公告)日：2007-01-09
申请号：US10367731
申请日：2003-02-17
申请人： Katsurou Sekiya , Hideaki Ishihara , Kyouichi Suzuki , Masahiro Kamiya
发明人： Katsurou Sekiya , Hideaki Ishihara , Kyouichi Suzuki , Masahiro Kamiya
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F9/4403
摘要： A microcomputer which is to be utilized in a condition of being built into an apparatus such as a vehicle ECU, includes a ROM having stored therein a program which is prepared by a user and a boot ROM which stores an initialization program for performing at least essential initialization processing which is required for all application programs that will be executed by the microcomputer. The need for the user to generate program contents relating to such initialization processing is thereby eliminated, while increased reliability of operation of the microcomputer is achieved. In addition, it is possible for user-specified initialization data to be read out from a user program and utilized in a part of the initialization processing of the initialization program.
摘要翻译：在车辆ECU等装置内置的微型计算机中，包括存储有由用户准备的程序的ROM和存储用于至少执行至少必要的初始化程序的引导ROM 由微型计算机执行的所有应用程序所需的初始化处理。从而消除了用户生成与这种初始化处理相关的节目内容的需要，同时实现了微型计算机的操作的可靠性的提高。此外，可以从用户程序读出用户指定的初始化数据，并在初始化程序的初始化处理的一部分中使用用户指定的初始化数据。

5. 发明申请

US20060155976A1 Processor, microcomputer and method for controlling program of microcomputer 有权
标题翻译：微机控制程序的处理器，微机及方法
公开(公告)号：US20060155976A1
公开(公告)日：2006-07-13
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgement instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgement instruction.
摘要翻译：微型计算机包括能够在并行分时操作中执行多个任务的CPU。这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映条件判决指示后的任务。

6. 发明申请

US20100017585A1 Microcomputer and encoding system for instruction code and CPU 有权
标题翻译：微机和编码系统的指令代码和CPU
公开(公告)号：US20100017585A1
公开(公告)日：2010-01-21
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

7. 发明申请

US20090204841A1 Periodic signal processing apparatus 有权
标题翻译：周期信号处理装置
公开(公告)号：US20090204841A1
公开(公告)日：2009-08-13
申请号：US12320800
申请日：2009-02-05
申请人： Akimasa Niwa , Masahiro Kamiya , Hideaki Ishihara , Yoshinori Teshima
发明人： Akimasa Niwa , Masahiro Kamiya , Hideaki Ishihara , Yoshinori Teshima
IPC分类号： G06F13/42
CPC分类号： G01D3/022
摘要： A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.
摘要翻译：用于处理从信号源输出的周期信号的信号处理装置具有中央处理单元和任务切换定时器。中央处理单元并行执行包括信号处理任务的多个任务。在信号处理任务中，中央处理单元在执行同步处理之后开始对周期信号进行处理以与周期信号同步，在完成同步处理之后将任务切换定时器设定到预定时间，完成同步处理后的中央处理单元。任务切换定时器在到期前立即停止中央处理单元的中断。任务切换定时器在到期时向中央处理单元输出任务切换信号，使得中央处理单元切换到信号处理任务。

8. 发明授权

US06934941B2 COMPILER FOR GENERATING RISC OBJECT CODE WHEREBY OPERATIONS ON BIT VARIABLES WRITTEN IN SOURCE CODE ARE EXECUTED BY PROCESSING BASED ON BIT JUDGEMENT OPERATIONS TO THEREBY REDUCE THE AMOUNT OF OBJECT CODE 失效
标题翻译：用于生成源代码上的字节变量上编写的RISC对象代码的编译器通过基于BIT判断操作的处理执行，以减少对象代码的数量
公开(公告)号：US06934941B2
公开(公告)日：2005-08-23
申请号：US09935686
申请日：2001-08-24
申请人： Masahiro Kamiya , Kunitaka Egawa , Hiroshi Matsuda , Hideaki Ishihara
发明人： Masahiro Kamiya , Kunitaka Egawa , Hiroshi Matsuda , Hideaki Ishihara
IPC分类号： G06F9/308 , G06F9/32 , G06F9/45
CPC分类号： G06F9/30018 , G06F8/443 , G06F9/30094
摘要： A computer program compiler generates object code to be executed by a RISC type of CPU, whereby in effect each bit operational expression appearing in the source code, such as an AND operation on two bit variables, is converted to an operation whereby the respective values of the bit variables which are operands of that expression are judged, and a specific binary value is assigned as the result of the bit operational expression based upon the judgement results, to thereby substantially reduce the number of RISC object code instructions corresponding to such an operation.
摘要翻译：计算机程序编译器生成要由RISC类型的CPU执行的目标代码，由此实际上出现在源代码中的每个位操作表达式（诸如对两个位变量的“与”操作）都被转换为一个操作，判断作为该表达式的操作数的位变量，并且基于判断结果来指定特定的二进制值作为比特操作表达式的结果，从而大大减少与这种操作相对应的RISC目标代码指令的数量。

9. 发明授权

US07991982B2 Microcomputer and encoding system for executing peripheral function instructions 有权
标题翻译：用于执行外围功能指令的微机和编码系统
公开(公告)号：US07991982B2
公开(公告)日：2011-08-02
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

10. 发明授权

US07664933B2 Microcomputer and encoding system for instruction code and CPU 有权
公开(公告)号：US07664933B2
公开(公告)日：2010-02-16
申请号：US11330237
申请日：2006-01-12
申请人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
发明人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.

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