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91. 发明授权

US06498096B2 Borderless contact to diffusion with respect to gate conductor and methods for fabricating 失效
标题翻译：与栅极导体无关的扩散接触和制造方法
公开(公告)号：US06498096B2
公开(公告)日：2002-12-24
申请号：US09800911
申请日：2001-03-08
申请人： James Allan Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Pekarik , Kirk David Peterson , Jed Hickory Rankin
发明人： James Allan Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Pekarik , Kirk David Peterson , Jed Hickory Rankin
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76888 , H01L27/11
摘要： A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.
摘要翻译：通过采用双重绝缘薄膜叠层作为掩模，提供了一种无边界的相对于栅极导体的扩散接触，用于限定整个芯片的栅极导体形状，并在限定栅极导体形状之后在暴露的导电层上提供相对较薄的损伤防止层。在一个实施例中，通过在衬底上形成绝缘层来提供无边界接触，在绝缘层上提供导电层，在导电层上提供第二绝缘层，在第二绝缘层上提供第三绝缘层，去除预选第二绝缘层和第三绝缘层的部分，在去除第二和第三绝缘层的那些区域中提供防损害层，去除第三绝缘层的预选部分，去除损坏防止层，去除导电层的暴露部分并且去除第二绝缘层的现在暴露部分。

92. 发明授权

US4556585A Vertically isolated complementary transistors 失效
标题翻译：垂直隔离互补晶体管
公开(公告)号：US4556585A
公开(公告)日：1985-12-03
申请号：US695716
申请日：1985-01-28
申请人： John R. Abernathey , Charles W. Koburger, III
发明人： John R. Abernathey , Charles W. Koburger, III
IPC分类号： H01L27/08 , H01L21/20 , H01L21/225 , H01L21/76 , H01L21/762 , H01L29/78 , B05D5/12
CPC分类号： H01L21/02381 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/2255 , H01L21/76294 , Y10S148/082
摘要： A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.
摘要翻译：一种在第一导电类型的外延层中制造互补晶体管器件的工艺，其通过在外延层中提供回填空腔而在N沟道晶体管和P沟道晶体管之间具有深垂直隔离侧壁，腔体的侧壁涂覆有材料层第一层是掺杂与外延层相同的导电类型的硅酸盐，外延层与外延层接触并用隔离扩散阻挡层涂覆，第二硅酸盐层被掺杂到与第一层相反的导电性并且被隔离通过所述隔离和扩散阻挡材料。用与外延层相反的导电类型的半导体材料回填空腔，并且在该回填操作期间，第一和第二层中的掺杂剂向外延伸进入外延层并且相当地扩散到回填材料中以防止寄生通道的产生。

93. 发明授权

US08847323B2 finFET devices 有权
标题翻译： finFET器件
公开(公告)号：US08847323B2
公开(公告)日：2014-09-30
申请号：US13613534
申请日：2012-09-13
申请人： Veeraraghavan S. Basker , David V. Horak , Hemanth Jagannathan , Charles W. Koburger, III
发明人： Veeraraghavan S. Basker , David V. Horak , Hemanth Jagannathan , Charles W. Koburger, III
IPC分类号： H01L29/66 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7845
摘要： A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
摘要翻译： FinFET结构及其制造方法具有降低的Ceff和增强的应力。 finFET结构包括多个finFET结构和形成栅极堆叠的一部分的应力材料，并且在多个finFET结构中的相邻空间之间的空间中。

94. 发明授权

US08846486B2 Deep well structures with single depth shallow trench isolation regions 有权
标题翻译：深井结构，具有单深度浅沟槽隔离区
公开(公告)号：US08846486B2
公开(公告)日：2014-09-30
申请号：US13418994
申请日：2012-03-13
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L21/761 , H01L21/8238 , H01L21/762 , H01L27/092
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.
摘要翻译：一种形成半导体器件的方法包括：在衬底中限定由一个或多个阱间STI结构分离的第一类型区域和第二类型区域; 蚀刻和填充在第一类型区域和第二类型区域中的至少一个区域中的一个或多个井下STI结构，用于隔离在相同极性阱内形成的半导体器件，其中形成一个或多个阱间STI结构相对于一个或多个井内STI结构基本相同的深度; 植入，主井区，其中主井区的底部设置在所述一个或多个井间和井内STI特征的底部之上; 以及植入，连接主井区域的一个或多个深井区域，其中所述一个或多个深井区域与所述一个或多个井间STI结构间隔开。

95. 发明授权

US08629008B2 Electrical isolation structures for ultra-thin semiconductor-on-insulator devices 有权
标题翻译：用于超薄绝缘体上半导体器件的电气隔离结构
公开(公告)号：US08629008B2
公开(公告)日：2014-01-14
申请号：US13348018
申请日：2012-01-11
申请人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/02
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译：在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。沉积至少一个接触电介质层。可以在接触通孔内形成与手柄基板电隔离的结构的接触。

96. 发明申请

US20130181261A1 BORDERLESS CONTACT STRUCTURE 有权
标题翻译：无边界接触结构
公开(公告)号：US20130181261A1
公开(公告)日：2013-07-18
申请号：US13348894
申请日：2012-01-12
申请人： VEERARAGHAVAN S. BASKER , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： VEERARAGHAVAN S. BASKER , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L29/78 , H01L21/28 , H01L21/20
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.
摘要翻译：公开了无边界接触结构或部分无边界接触结构和制造方法。该方法包括在栅极结构内形成栅极结构和由间隔物限定的空间。该方法还包括在该空间中，在栅极结构上和半导体材料上覆盖密封材料。该方法还包括从栅极结构和半导体材料上方移除密封材料，将密封材料留在空间内。该方法还包括在栅极结构上形成层间电介质材料。该方法进一步包括图案化层间电介质材料以形成暴露半导体材料和栅极结构的一部分的开口。该方法还包括在形成在层间电介质材料中的开口中形成接触。

97. 发明申请

US20130175622A1 ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：用于超薄半导体绝缘体器件的电气隔离结构
公开(公告)号：US20130175622A1
公开(公告)日：2013-07-11
申请号：US13348018
申请日：2012-01-11
申请人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译：在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。沉积至少一个接触电介质层。可以在接触通孔内形成与手柄基板电隔离的结构的接触。

98. 发明授权

US08349674B2 Forming borderless contact for transistors in a replacement metal gate process 有权
标题翻译：在替代金属栅极工艺中形成晶体管的无边界接触
公开(公告)号：US08349674B2
公开(公告)日：2013-01-08
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供了形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

99. 发明申请

US20120329275A1 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
公开(公告)号：US20120329275A1
公开(公告)日：2012-12-27
申请号：US13607677
申请日：2012-09-08
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

100. 发明申请

US20120248508A1 FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS 有权
标题翻译：在替代金属门过程中形成晶体管的无边界接触
公开(公告)号：US20120248508A1
公开(公告)日：2012-10-04
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供一种形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

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