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91. 再颁专利

USRE44376E1 Silicon substrate with reduced surface roughness 有权
标题翻译：具有降低表面粗糙度的硅衬底
公开(公告)号：USRE44376E1
公开(公告)日：2013-07-16
申请号：US13117881
申请日：2011-05-27
申请人： Gwo-Yuh Shiau , Ming Chyi Liu , Tzu-Hsuan Hsu , Chia-Shiung Tsai
发明人： Gwo-Yuh Shiau , Ming Chyi Liu , Tzu-Hsuan Hsu , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L21/268 , H01L27/1464 , H01L27/14683
摘要： The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer.
摘要翻译：本公开提供一种制造半导体器件的方法，包括提供包括第一表面和第二表面的半导体衬底，其中至少一个成像传感器位于第一表面附近，激活邻近第二表面的半导体衬底中的掺杂剂层使用局部退火工艺，并蚀刻掺杂剂层。

92. 发明授权

US08436443B2 Backside depletion for backside illuminated image sensors 有权
标题翻译：背面照明图像传感器的背面耗尽
公开(公告)号：US08436443B2
公开(公告)日：2013-05-07
申请号：US12107199
申请日：2008-04-22
申请人： Tzu-Hsuan Hsu , Han-Chi Liu , Ching-Chun Wang
发明人： Tzu-Hsuan Hsu , Han-Chi Liu , Ching-Chun Wang
IPC分类号： H01L27/146 , H01L31/09
CPC分类号： H01L31/0232 , H01L27/14603 , H01L27/1464 , H01L27/14683
摘要： A backside illuminated image sensor is provided which includes a substrate having a front side and a backside, a sensor formed in the substrate at the front side, the sensor including at least a photodiode, and a depletion region formed in the substrate at the backside, a depth of the depletion region is less than 20% of a thickness of the substrate.
摘要翻译：提供了背面照明图像传感器，其包括具有前侧和后侧的基板，形成在前侧的基板中的传感器，所述传感器至少包括光电二极管，以及在背面形成在基板中的耗尽区域，耗尽区的深度小于衬底厚度的20％。

93. 发明申请

US20120280357A1 Method of Forming an Isolation Structure 有权
标题翻译：形成隔离结构的方法
公开(公告)号：US20120280357A1
公开(公告)日：2012-11-08
申请号：US13552734
申请日：2012-07-19
申请人： Ching-Chun Wang , Tzu-Hsuan Hsu
发明人： Ching-Chun Wang , Tzu-Hsuan Hsu
IPC分类号： H01L27/06
CPC分类号： H01L23/522 , H01L21/6836 , H01L21/76256 , H01L21/76898 , H01L23/53223 , H01L23/53238 , H01L2221/6834 , H01L2924/0002 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，在半导体衬底的正面形成第一电路和第二电路，将半导体衬底的正面粘合到载体衬底，从背面减薄半导体衬底，并且从半导体衬底的背侧到前侧形成沟槽，以将第一电路与第二电路隔离。

94. 发明授权

US08304354B2 Methods to avoid laser anneal boundary effect within BSI CMOS image sensor array 有权
标题翻译： BSI CMOS图像传感器阵列中避免激光退火边界效应的方法
公开(公告)号：US08304354B2
公开(公告)日：2012-11-06
申请号：US12765496
申请日：2010-04-22
申请人： Kai-Chun Hsu , Yeur-Luen Tu , Chung Chien Wang , Tzu-Hsuan Hsu , Ching-Chun Wang
发明人： Kai-Chun Hsu , Yeur-Luen Tu , Chung Chien Wang , Tzu-Hsuan Hsu , Ching-Chun Wang
IPC分类号： H01L21/31
CPC分类号： H01L27/14698 , H01L21/268 , H01L27/1464 , H01L27/14643
摘要： Methods are disclosed herein for determining the laser beam size and the scan pattern of laser annealing when fabricating backside illumination (BSI) CMOS image sensors to keep dark-mode stripe patterns corresponding to laser scan boundary effects from occurring within the sensor array regions of the image sensors. Each CMOS image sensor has a sensor array region and a periphery circuit. The methods determines a size of the laser beam from a length of the sensor array region and a length of the periphery circuit so that the laser beam covers an integer number of the sensor array region for at least one alignment of the laser beam on the array of BSI image sensors. The methods further determines a scan pattern so that the boundary of the laser beam does not overlap the sensor array regions during the laser annealing, but only overlaps the periphery circuits.
摘要翻译：本文公开了用于确定当制造背面照明（BSI）CMOS图像传感器以保持对应于激光扫描边界效应的暗模式条纹图案在图像的传感器阵列区域内发生的激光退火的激光束尺寸和扫描图案的方法传感器。每个CMOS图像传感器具有传感器阵列区域和外围电路。该方法确定来自传感器阵列区域的长度和外围电路的长度的激光束的尺寸，使得激光束覆盖整数个传感器阵列区域，用于激光束在阵列上的至少一个对准的BSI图像传感器。该方法进一步确定扫描图案，使得激光束的边界在激光退火期间不与传感器阵列区域重叠，而仅与外围电路重叠。

95. 发明授权

US08252654B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US08252654B2
公开(公告)日：2012-08-28
申请号：US12942312
申请日：2010-11-09
申请人： Tzu-Hsuan Hsu , Hang-Ting Lue
发明人： Tzu-Hsuan Hsu , Hang-Ting Lue
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/66833 , H01L29/792
摘要： In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.
摘要翻译：在存储单元的制造方法中，设置有基板。在基板的表面附近形成具有第一导电类型的掺杂区域。去除衬底的一部分以在衬底中限定多个鳍结构。在翅片结构之间形成多个隔离结构。隔离结构的表面低于翅片结构的表面。栅极结构形成在衬底上并跨越翅片结构。栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。

96. 发明授权

US08247882B2 Method of forming an isolation structure 有权
标题翻译：形成隔离结构的方法
公开(公告)号：US08247882B2
公开(公告)日：2012-08-21
申请号：US13009354
申请日：2011-01-19
申请人： Ching-Chun Wang , Tzu-Hsuan Hsu
发明人： Ching-Chun Wang , Tzu-Hsuan Hsu
IPC分类号： H01L29/00
CPC分类号： H01L23/522 , H01L21/6836 , H01L21/76256 , H01L21/76898 , H01L23/53223 , H01L23/53238 , H01L2221/6834 , H01L2924/0002 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，在半导体衬底的正面形成第一电路和第二电路，将半导体衬底的正面粘合到载体衬底，从背面减薄半导体衬底，并且从半导体衬底的背侧到前侧形成沟槽，以将第一电路与第二电路隔离。

97. 发明授权

US08030721B2 Method to optimize substrate thickness for image sensor device 有权
标题翻译：优化图像传感器设备基板厚度的方法
公开(公告)号：US08030721B2
公开(公告)日：2011-10-04
申请号：US12904903
申请日：2010-10-14
申请人： Tzu-Hsuan Hsu , Alex Hsu , Ching-Chun Wang
发明人： Tzu-Hsuan Hsu , Alex Hsu , Ching-Chun Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/14689 , H01L21/26513 , H01L27/1463
摘要： Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.
摘要翻译：提供一种制造图像传感器装置的方法，该图像传感器装置包括提供具有正面和背面的基板; 在衬底的前侧上形成光致抗蚀剂以限定具有第一宽度的开口，光致抗蚀剂具有与第一宽度相关的第一厚度; 通过使用与第一厚度相关的注入能量通过开口执行注入工艺，从而形成第一掺杂隔离特征; 形成与所述第一掺杂隔离特征相邻的光感测特征，所述光感测特征具有第二宽度; 以及从背面使衬底变薄，使得衬底具有不超过第一掺杂隔离特征深度的两倍的第二厚度。像素尺寸基本上等于第一和第二宽度。

98. 发明授权

US08022466B2 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same 有权
标题翻译：具有含多晶硅的多层绝缘结构的非易失性存储单元，包括其的存储器阵列及其操作方法
公开(公告)号：US08022466B2
公开(公告)日：2011-09-20
申请号：US11588830
申请日：2006-10-27
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

99. 发明申请

US20110012192A1 Vertical Channel Transistor Structure and Manufacturing Method Thereof 审中-公开
标题翻译：垂直沟道晶体管的结构及制造方法
公开(公告)号：US20110012192A1
公开(公告)日：2011-01-20
申请号：US12892044
申请日：2010-09-28
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

100. 发明申请

US20100290293A1 METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME 审中-公开
标题翻译：通过边界读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20100290293A1
公开(公告)日：2010-11-18
申请号：US12845064
申请日：2010-07-28
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

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