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91. 发明申请

US20100155850A1 TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS 有权
标题翻译：通过记录泄漏和源区域向通道区域提供紧密接近的晶体管中的应力源的技术
公开(公告)号：US20100155850A1
公开(公告)日：2010-06-24
申请号：US12710744
申请日：2010-02-23
申请人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann , Peter Javorka , Joe Bloomquist
发明人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann , Peter Javorka , Joe Bloomquist
IPC分类号： H01L27/092
CPC分类号： H01L29/66628 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/7843 , H01L29/7848 , H01L29/78621 , H01L29/78684
摘要： By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
摘要翻译：通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

92. 发明授权

US07723195B2 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US07723195B2
公开(公告)日：2010-05-25
申请号：US11566287
申请日：2006-12-04
申请人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
发明人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L29/165 , H01L29/66583 , H01L29/7834 , H01L29/7848
摘要： A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
摘要翻译：形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。在半导体材料的双轴应变层上形成栅电极。在栅电极附近形成凸起的源区和升高的漏极区。将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

93. 发明授权

US07719060B2 Tensile strain source using silicon/germanium in globally strained silicon 有权
标题翻译：在全球应变硅中使用硅/锗的拉伸应变源
公开(公告)号：US07719060B2
公开(公告)日：2010-05-18
申请号：US12112288
申请日：2008-04-30
申请人： Andy Wei , Karla Romero , Manfred Horstmann
发明人： Andy Wei , Karla Romero , Manfred Horstmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7848 , H01L29/7849 , H01L29/78684
摘要： By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
摘要翻译：通过将硅/锗混合物嵌入到高拉伸应变的硅层中，可以在硅/锗混合物中保持适度高的拉伸应变程度，从而可以在硅/锗材料的基础上提高N沟道晶体管的性能。在其他区域，可以改变锗浓度以提供不同水平的拉伸或压缩应变。

94. 发明申请

US20100090321A1 HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS 审中-公开
标题翻译：用于在晶体管制造期间形成电介质材料的减小厚度的高K蚀刻层
公开(公告)号：US20100090321A1
公开(公告)日：2010-04-15
申请号：US12248971
申请日：2008-10-10
申请人： Robert Mulfinger , Andy Wei , Roman Boschke , Casey Scott
发明人： Robert Mulfinger , Andy Wei , Roman Boschke , Casey Scott
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76826 , H01L21/76829 , H01L21/76837 , H01L29/517 , H01L29/7843
摘要： By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material.
摘要翻译：通过提供高k电介质蚀刻停止材料作为用于图案化层间电介质材料的蚀刻停止层，可以实现增强的性能和更高的柔性，这是因为例如增加量的高应力介电材料可以更接近于相应的晶体管由于高k电介质蚀刻停止材料的厚度减小。

95. 发明申请

US20090057809A1 STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY PROVIDING A STRESSED DIELECTRIC LAYER ABOVE A STRESS-NEUTRAL DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE 有权
标题翻译：通过在半导体器件中提供应力中性介电材料上的应力介电层在介电层中的应力传递
公开(公告)号：US20090057809A1
公开(公告)日：2009-03-05
申请号：US12045095
申请日：2008-03-10
申请人： Ralf Richter , Andy Wei , Manfred Horstmann , Joerg Hohage
发明人： Ralf Richter , Andy Wei , Manfred Horstmann , Joerg Hohage
IPC分类号： H01L21/31 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L29/7843
摘要： By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.
摘要翻译：通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

96. 发明申请

US20090057769A1 CMOS DEVICE HAVING GATE INSULATION LAYERS OF DIFFERENT TYPE AND THICKNESS AND A METHOD OF FORMING THE SAME 有权
标题翻译：具有不同类型和厚度的门绝缘层的CMOS器件及其形成方法
公开(公告)号：US20090057769A1
公开(公告)日：2009-03-05
申请号：US12049548
申请日：2008-03-17
申请人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
发明人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/82345 , H01L21/823462 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/088 , H01L27/0922 , H01L29/66545 , H01L29/7843 , H01L29/7848 , Y10S438/926
摘要： In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
摘要翻译：在通过高k金属栅极结构代替常规栅电极结构的工艺顺序中，例如通过使用高选择性蚀刻步骤，附加掩模步骤的数量可以保持在低水平，从而保持与常规栅极结构的高度兼容性 CMOS技术。此外，本文公开的技术使得能够与前端处理技术和后端处理技术兼容，从而允许将已建立的应变诱发机制集成在晶体管级以及接触级中。

97. 发明申请

US20080237712A1 SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO 有权
标题翻译：具有减少长度的漏极和源极区域的SOI晶体管和受压介电材料相邻
公开(公告)号：US20080237712A1
公开(公告)日：2008-10-02
申请号：US11936855
申请日：2007-11-08
申请人： Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
发明人： Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.
摘要翻译：通过在SOI晶体管的漏极和源极区域中形成的凹槽中重新配置材料，在形成相应的金属硅化物区域之前，可以将凹槽的深度增加到掩埋绝缘层，从而当对应的金属硅化物区域时减小串联电阻并增强应力传递晶体管元件被高应力介电材料覆盖。材料再分配可以基于高温氢气烘烤来实现。

98. 发明申请

US20080203427A1 SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE 有权
标题翻译：具有应变半导体合金浓度分布的半导体器件
公开(公告)号：US20080203427A1
公开(公告)日：2008-08-28
申请号：US11866461
申请日：2007-10-03
申请人： Anthony Mowry , Bernhard Trui , Maciej Wiatr , Andreas Gehring , Andy Wei
发明人： Anthony Mowry , Bernhard Trui , Maciej Wiatr , Andreas Gehring , Andy Wei
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/165 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/6653 , H01L29/66636 , H01L29/7848 , H01L29/78618
摘要： A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover.
摘要翻译：一种新技术能够提供具有高应力诱导区域的应力诱导合金和可通过适用于商业大容量半导体器件制造环境的标准加工步骤加工的区域。这些区域可以通过具有变化的生长材料组成的生长过程或通过诸如离子注入的其它方法形成。在晶体管的沟道区附近的高应力诱导区域可以被适当的覆盖层覆盖。

99. 发明授权

US07399663B2 Embedded strain layer in thin SOI transistors and a method of forming the same 有权
标题翻译：薄SOI晶体管中的嵌入式应变层及其形成方法
公开(公告)号：US07399663B2
公开(公告)日：2008-07-15
申请号：US11466572
申请日：2006-08-23
申请人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
发明人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L29/78684 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.
摘要翻译：通过形成通过掩埋绝缘层的深凹槽并重新生长应变半导体材料，可以在SOI类晶体管中提供增强的应变产生机制。因此，也可以通过整个有源层上的嵌入的应变半导体材料有效地产生应变，从而显着提高可以限定两个沟道区的晶体管器件的性能。

100. 发明授权

US07354839B2 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same 有权
标题翻译：栅极结构和具有不对称间隔元件的晶体管及其形成方法
公开(公告)号：US07354839B2
公开(公告)日：2008-04-08
申请号：US11247367
申请日：2005-10-11
申请人： Andy Wei , Gert Burbach , David Greenlaw
发明人： Andy Wei , Gert Burbach , David Greenlaw
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823864 , H01L29/66772 , H01L29/7835
摘要： Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.
摘要翻译：公开了形成非对称栅极结构的方法，其包括设置在栅电极的相对侧上且具有不同宽度的间隔元件。采用不对称栅结构来形成使用对称注入方案的场效应晶体管的晕区和扩展区的非对称设计，或进一步提高非对称注入方案的有效性。对于给定的基本晶体管架构，晶体管的性能可以显着提高。特别地，由于提供卤素区域，可能在源极侧产生具有PN结的陡峭浓度梯度的大的重叠区域，而漏极重叠可以被显着地减少或者甚至可以被完全避免以进一步增强晶体管性能。

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