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91. 发明授权

US07384837B2 Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications 有权
标题翻译：在应变硅CMOS应用中分离硅锗位错区的方法
公开(公告)号：US07384837B2
公开(公告)日：2008-06-10
申请号：US11073185
申请日：2005-03-03
申请人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
发明人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L27/1203 , H01L29/78645
摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forms a layer of strained-Si overlying the first and second SiGe layers; forms a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forms an p-well in the substrate and the overlying first layer of SiGe; forming forms a p-well in the substrate and the overlying second layer of SiGe; forms channel regions, in the strained-Si, and forms PMOS and NMOS transistor source and drain regions.
摘要翻译：提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。该方法形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成覆盖衬底并且邻近第一SiGe层的第二层松弛SiGe，其厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于第一SiGe层和第二SiGe层之间的浅沟槽隔离区; 在衬底和SiGe的上覆第一层中形成p阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

92. 发明授权

US07378309B2 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US07378309B2
公开(公告)日：2008-05-27
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

93. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

94. 发明授权

US07358160B2 Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer 有权
标题翻译：用硅纳米线缓冲层选择性形成硅化合物半导体晶片的方法
公开(公告)号：US07358160B2
公开(公告)日：2008-04-15
申请号：US11481437
申请日：2006-07-06
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/36
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02529 , H01L21/02538 , H01L21/7624
摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where X≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.
摘要翻译：提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。该方法形成Si衬底。在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。化合物半导体选择性沉积在Si纳米线尖端上。横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或Si X N Y ，其中 X <= 3 AND Y <= 4。化合物半导体可以是GaN，GaAs，GaAlN或SiC。在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

95. 发明申请

US20080067499A1 Silicon/germanium superlattice thermal sensor 失效
公开(公告)号：US20080067499A1
公开(公告)日：2008-03-20
申请号：US11522003
申请日：2006-09-15
申请人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L31/035254 , B82Y20/00 , H01L27/14649 , H01L31/028 , H01L31/101 , H01L31/1804 , Y02P70/521
摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

96. 发明授权

US07297602B2 Conductive metal oxide gate ferroelectric memory transistor 失效
标题翻译：导电金属氧化物栅极铁电存储晶体管
公开(公告)号：US07297602B2
公开(公告)日：2007-11-20
申请号：US10659547
申请日：2003-09-09
申请人： Sheng Teng Hsu , Tingkai Li
发明人： Sheng Teng Hsu , Tingkai Li
IPC分类号： H01L21/331 , H01L21/335
CPC分类号： G11C11/22 , H01L21/28273 , H01L21/28291 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

97. 发明申请

US20070218580A1 Triple-junction filterless CMOS imager cell 失效
标题翻译：三联无滤膜CMOS成像单元
公开(公告)号：US20070218580A1
公开(公告)日：2007-09-20
申请号：US11580407
申请日：2006-10-13
申请人： Sheng Teng Hsu , Jong-Jan Lee
发明人： Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/14632 , H01L27/14645 , H01L27/14647 , H01L27/14683 , H01L27/14689
摘要： A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.
摘要翻译：提供三结互补金属氧化物半导体（CMOS）无滤色器彩色成像器单元。成像器单元由体硅（Si）衬底制成。在Si衬底中形成包括第一，第二和第三光电二极管的光电二极管组作为三结结构。晶体管组连接到光电二极管组，并检测每个光电二极管的独立输出信号。通常，晶体管组形成在衬底的顶表面中。例如，Si衬底可以是p掺杂的Si衬底，并且光电二极管三结结构包括第一光电二极管，其形成从Si衬底顶表面处的n +掺杂区域到下一个p掺杂区域的pn结。第二光电二极管形成从p掺杂区域到下面的n阱的pn结，并且第三光电二极管形成从n阱到下面的p掺杂Si衬底的pn结。

98. 发明授权

US07255745B2 Iridium oxide nanowires and method for forming same 失效
标题翻译：氧化铱纳米线及其形成方法
公开(公告)号：US07255745B2
公开(公告)日：2007-08-14
申请号：US10971330
申请日：2004-10-21
申请人： Fengyan Zhang , Robert A. Barrowcliff , Sheng Teng Hsu
发明人： Fengyan Zhang , Robert A. Barrowcliff , Sheng Teng Hsu
IPC分类号： C30B29/62
CPC分类号： H01L24/48 , C30B25/005 , C30B29/16 , C30B29/62 , H01L24/45 , H01L24/49 , H01L2224/05644 , H01L2224/05655 , H01L2224/05669 , H01L2224/43827 , H01L2224/45015 , H01L2224/45144 , H01L2224/45155 , H01L2224/45157 , H01L2224/45166 , H01L2224/45169 , H01L2224/45178 , H01L2224/45181 , H01L2224/45565 , H01L2224/45599 , H01L2224/45688 , H01L2224/48011 , H01L2224/48091 , H01L2224/4813 , H01L2224/48463 , H01L2224/4847 , H01L2224/48599 , H01L2224/49111 , H01L2224/49175 , H01L2924/00011 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/10271 , H01L2924/1033 , H01L2924/10335 , H01L2924/14 , H01L2924/20751 , Y10S977/762 , Y10S977/763 , Y10S977/811 , H01L2924/00014 , H01L2924/20651 , H01L2924/00 , H01L2924/01006
摘要： Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 Å, a length in the range of 1000 Å to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 Å.
摘要翻译：提供氧化铱（IrOx）纳米线和形成纳米线的方法。该方法包括：提供具有0.5至5纳米（nm）范围内的厚度的非连续表面的生长促进膜，并由诸如Ti，Co，Ni，Au，Ta，多晶硅多晶硅），SiGe，Pt，Ir，TiN或TaN; 建立200〜600℃的基板温度。引入氧气作为前体反应气体; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 使用金属有机化学气相沉积（MOCVD）工艺，从生长促进膜表面生长IrOx纳米线。 IrOx纳米线的直径在100至1000埃的范围内，长度在1000埃至2微米之间，纵横比（长宽比）大于50:1。此外，纳米线包括覆盖有厚度小于Å的非晶层的单晶纳米线芯。

99. 发明授权

US07247530B2 Ultrathin SOI transistor and method of making the same 失效
标题翻译：超薄SOI晶体管及其制作方法
公开(公告)号：US07247530B2
公开(公告)日：2007-07-24
申请号：US11050495
申请日：2005-02-01
申请人： Sheng Teng Hsu , Jong-Jan Lee
发明人： Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/66772 , Y10S438/926
摘要： A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.
摘要翻译：制造超薄SOI存储晶体管的方法包括：制备衬底，包括形成衬底的超薄SOI层; 调整SOI层的阈值电压; 在SOI层上沉积一层氧化硅; 图案化和蚀刻氧化硅层以在栅极区域中形成牺牲氧化物栅极; 沉积氮化硅层并将氮化硅形成用于牺牲氧化物栅极的氮化硅侧壁; 沉积和平滑一层非晶硅; 选择性地蚀刻牺牲栅极氧化物; 在栅极区生长一层氧化物; 沉积和平滑第二层非晶硅; 图案化和蚀刻第二层非晶硅; 注入离子以形成源区和漏区; 退火结构; 并沉积一层钝化氧化物。

100. 发明授权

US07226504B2 Method to form thick relaxed SiGe layer with trench structure 失效
标题翻译：形成具有沟槽结构的厚松弛SiGe层的方法
公开(公告)号：US07226504B2
公开(公告)日：2007-06-05
申请号：US10062336
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B33/02
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L21/324
摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
摘要翻译：形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

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