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91. 发明授权

US5412262A Semiconductor integrated circuit device having plurality of supply potential lines connected thereto, and system employing the same 失效
标题翻译：具有与其连接的多个电源电位线的半导体集成电路器件及其系统
公开(公告)号：US5412262A
公开(公告)日：1995-05-02
申请号：US279626
申请日：1994-07-25
申请人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
发明人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
IPC分类号： H03K19/00 , H01L27/02 , H03K19/0175 , H03K19/0185 , H03K19/02
CPC分类号： H03K19/017527 , H03K19/018521 , H01L27/0214
摘要： In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.
摘要翻译：在其中多个半导体集成电路器件共存并且其中布置多条电源线的系统中，TTL接口LSI和ECL接口LSI的主电源被共享，以便减少电源电位线的数量。此外，在与例如TTL和ECL接口LSI接口的BiCMOS LSI的LSI具有约3V的器件耐受电压的情况下，允许与两者的两端的电源电压| 5V | 的TTL接口LSI的主电源和电源电压| 2 V | 由于电源电压具有3V的差异，所以ECL接口LSI的射极跟随器部分的电源。

92. 发明授权

US5378904A Semiconductor integrated circuit and method and system for designing layout of the same 失效
标题翻译：半导体集成电路及其设计方法及系统设计
公开(公告)号：US5378904A
公开(公告)日：1995-01-03
申请号：US760888
申请日：1991-09-17
申请人： Goro Suzuki , Masahiro Iwamura , Tetsuya Yamamoto , Yoshio Okamura
发明人： Goro Suzuki , Masahiro Iwamura , Tetsuya Yamamoto , Yoshio Okamura
IPC分类号： H01L21/82 , H01L27/02
CPC分类号： H01L27/0207
摘要： An LSI layout design method is for placing on a chip a plurality of different master cells, each of which has a plurality of signal wiring conductors not connected to internal elements, for example, transistors, resistors and so on for realizing a certain logic function.
摘要翻译： LSI布局设计方法是将多个不同的主单元放置在芯片上，每个主单元具有不连接到内部元件的多个信号布线导体，例如晶体管，电阻器等，以实现某种逻辑功能。

93. 发明授权

US5339448A Microprocessor with improved internal transmission 失效
标题翻译：微处理器具有改进的内部传输
公开(公告)号：US5339448A
公开(公告)日：1994-08-16
申请号：US015296
申请日：1993-01-22
申请人： Shigeya Tanaka , Masahiro Iwamura , Tatsumi Yamauchi , Tatsuo Nojiri , Hisashi Tada , Tetsuo Nakano
发明人： Shigeya Tanaka , Masahiro Iwamura , Tatsumi Yamauchi , Tatsuo Nojiri , Hisashi Tada , Tetsuo Nakano
IPC分类号： G06F7/00 , G06F13/16 , G06F13/36 , G06F13/40 , G06F15/78 , G06F13/38
CPC分类号： G06F13/1684 , G06F13/4027 , G06F13/4072
摘要： A microprocessor according to the present invention comprises a sub-read bus, to which output terminals of registers of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus of the microprocessor through a bus output circuit. Upon occurrence of a read access to any of the registers, the bus output circuit couples the sub-read bus with the main read bus, whereby data read out from the registers to the sub-read bus are transmitted to the main read bus, and under no existence of the read access, the bus output circuit interrupts the data transmission from the sub-read bus to the main read bus. With this, a load capacitance of the read bus is reduced. As a result, a time for making access to the read bus is much improved.
摘要翻译：根据本发明的微处理器包括子读总线，微处理器的寄存器文件的寄存器的输出端耦合到该子读总线。子读取总线又通过总线输出电路耦合到微处理器的主读取总线。在发生对任何寄存器的读取访问时，总线输出电路将子读总线与主读总线耦合，由此从寄存器读出到子读总线的数据被发送到主读总线，在不存在读访问的情况下，总线输出电路中断从子读总线到主读总线的数据传输。因此，读总线的负载电容减小。结果，访问读总线的时间大大改善。

94. 发明授权

US5133064A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5133064A
公开(公告)日：1992-07-21
申请号：US184782
申请日：1988-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

95. 发明授权

US5117382A Semiconductor integrated circuit for performing an arithmetic operation including bipolar and MOS transistors 失效
标题翻译：用于执行包括双极和MOS晶体管在内的算术运算的半导体集成电路
公开(公告)号：US5117382A
公开(公告)日：1992-05-26
申请号：US618114
申请日：1990-11-26
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

96. 发明授权

US5047669A Tristate circuit using bipolar transistor and CMOS transistor 失效
标题翻译：三态电路采用双极晶体管和CMOS晶体管
公开(公告)号：US5047669A
公开(公告)日：1991-09-10
申请号：US318689
申请日：1989-03-03
申请人： Masahiro Iwamura , Kozaburo Kurita , Hideo Maejima , Tetsuo Nakano , Atsuo Hotta
发明人： Masahiro Iwamura , Kozaburo Kurita , Hideo Maejima , Tetsuo Nakano , Atsuo Hotta
IPC分类号： H03K17/567 , H03K19/003 , H03K19/0175 , H03K19/08 , H03K19/094 , H03K19/0944
CPC分类号： H03K17/567 , H03K19/00307 , H03K19/09429 , H03K19/09448
摘要： In a semiconductor integrated circuit, drain-source paths of an NMOS transistor and a PMOS transistor are connected between the base and emitter of a bipolar transistor, and control signals are applied to gates of the NMOS transistor and the PMOS transistor so as to keep the NMOS transistor and the PMOS transistor at OFF condition when the bipolar transistor is operating and so as to keep the NMOS transistor and the PMOS transistor at ON condition when the bipolar transistor is in the quiescent state.

97. 发明授权

US4983862A Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block 失效
标题翻译：具有用于向内部逻辑块提供输入信号的双MOS输入电路的半导体集成电路
公开(公告)号：US4983862A
公开(公告)日：1991-01-08
申请号：US429489
申请日：1989-10-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

98. 发明授权

US4879480A Bicmos gate array 失效
标题翻译：二门门阵列
公开(公告)号：US4879480A
公开(公告)日：1989-11-07
申请号：US240450
申请日：1988-09-02
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

99. 发明授权

US4849658A Dynamic logic circuit including bipolar transistors and field-effect transistors 失效
标题翻译：动态逻辑电路包括双极晶体管和场效应晶体管
公开(公告)号：US4849658A
公开(公告)日：1989-07-18
申请号：US81696
申请日：1987-08-04
申请人： Masahiro Iwamura , Takashi Hotta , Hideo Maejima
发明人： Masahiro Iwamura , Takashi Hotta , Hideo Maejima
IPC分类号： H03K19/08 , G06F7/50 , G06F7/501 , G11C7/12 , H03K19/096 , H03K19/177
CPC分类号： G06F7/5016 , G11C7/12 , H03K19/0963 , H03K19/1772 , G06F2207/3872
摘要： A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.
摘要翻译：提供了一种实现高速运行的动态逻辑电路。提供至少一个具有集电极，基极和发射极的双极晶体管，其中集电极 - 发射极电流路径连接在动态逻辑电路的输出端和第一电位之间。预充电装置耦合在第二电位和动态逻辑电路的输出端之间，以根据周期性地改变其状态的至少一个时钟信号对输出进行预充电。此外，提供了至少两个场效应晶体管，其中响应于时钟信号而假定与预充电装置相反的导通或截止状态，而另一个响应于至少一个输入信号而工作。两个场效应晶体管的源极 - 漏极电流路径连接在动态逻辑电路的输出端和双极晶体管的基极之间。

100. 发明授权

US4769561A Bipolar transistor-field effect transistor composite circuit 失效
标题翻译：双极晶体管场效应晶体管复合电路
公开(公告)号：US4769561A
公开(公告)日：1988-09-06
申请号：US680495
申请日：1984-12-11
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/01 , H03K17/567 , H03K17/687 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.
摘要翻译：提供了双极晶体管 - 互补场效应晶体管复合电路，其包括一对第一和第二双极晶体管，每个具有第一导电类型的集电极，第二导电类型的基极和第一导电类型的发射极。双极晶体管的集电极 - 发射极电流路径在第一和第二电位之间彼此串联连接，连接节点提供复合电路的输出。场效应晶体管分别耦合在双极晶体管的基极和集电极之间，用于响应于提供给复合电路的输入信号而彼此相反地控制双极晶体管的导通截止状态。此外，为第一和第二双极晶体管的基极提供放电布置，以在第一和第二双极晶体管的基极中的寄生电容被截止时放电。

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