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91. 发明授权

US08737134B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08737134B2
公开(公告)日：2014-05-27
申请号：US13417719
申请日：2012-03-12
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
摘要翻译：根据实施例的非易失性半导体存储装置包括驱动电路。将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线电压和第一选择线电压。

92. 发明授权

US08405139B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
公开(公告)号：US08405139B2
公开(公告)日：2013-03-26
申请号：US13085884
申请日：2011-04-13
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

93. 发明授权

US08344442B2 Nonvolatile semiconductor memory having a gate electrode with a round-arched shape 有权
标题翻译：具有圆弧形状的栅电极的非易失性半导体存储器
公开(公告)号：US08344442B2
公开(公告)日：2013-01-01
申请号：US13365604
申请日：2012-02-03
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.
摘要翻译：一种非易失性半导体存储器制造方法，包括在半导体衬底上形成第一绝缘膜和浮栅电极材料; 通过蚀刻第一绝缘膜和浮栅电极材料分别形成栅绝缘膜和浮栅电极，并通过蚀刻半导体衬底形成用于元件隔离区的沟槽; 以及通过在所述沟槽中埋入第二绝缘膜并使所述第二绝缘膜平坦化来形成元件区域和所述元件隔离区域。

94. 发明授权

US08316063B2 Data-driven database processor 有权
标题翻译：数据驱动的数据库处理器
公开(公告)号：US08316063B2
公开(公告)日：2012-11-20
申请号：US12812016
申请日：2008-12-24
申请人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
发明人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
IPC分类号： G06F7/00
CPC分类号： G06F17/3051 , G06F17/30371 , G06F17/30595
摘要： Provided is a technique for a data-driven database which frees a user from having to be conscious of a sequence in which instructions of a program for accessing a database are described, an interrelation of data items, and the like, and from having to describe redundant instructions. A data-driven database processor includes: schema definition storage means 2 for storing a schema definition of a database 24; derived definition storage means 3 for storing a derived definition describing a cause-and-effect relationship that exists when a value of a given data item is derived from a value of another data item; derived definition processing means 26 for generating a trigger program 27 that makes a chain of changes to values of data items based on the cause-and-effect relationship described in the derived definition; and a database management system 23 for executing the trigger program 27 when a change is made to the other data item that affects the value of the given data item.
摘要翻译：提供了一种用于数据驱动数据库的技术，其释放用户不必意识到描述用于访问数据库的程序的指令，数据项的相关性等的序列，并且不必描述冗余指令。数据驱动数据库处理器包括：用于存储数据库24的模式定义的模式定义存储装置2; 派生定义存储装置3，用于存储描述当从另一数据项的值导出给定数据项的值时存在的因果关系的派生定义; 导出定义处理装置26，用于基于导出的定义中描述的因果关系，产生触发程序27，触发程序27使数据项的值变化链; 以及数据库管理系统23，用于当对影响给定数据项的值的其他数据项进行改变时，执行触发程序27。

95. 发明申请

US20120168846A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20120168846A1
公开(公告)日：2012-07-05
申请号：US13421248
申请日：2012-03-15
申请人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11548 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L29/788
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

96. 发明授权

US08134199B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08134199B2
公开(公告)日：2012-03-13
申请号：US12917906
申请日：2010-11-02
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.
摘要翻译：一种非易失性半导体存储器制造方法，包括在半导体衬底上形成第一绝缘膜和浮栅电极材料; 通过蚀刻第一绝缘膜和浮栅电极材料分别形成栅绝缘膜和浮栅电极，并通过蚀刻半导体衬底形成用于元件隔离区的沟槽; 以及通过在所述沟槽中埋入第二绝缘膜并使所述第二绝缘膜平坦化来形成元件区域和所述元件隔离区域。

97. 发明申请

US20110210947A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION RECORDING MEDIUM, AND PROGRAM 有权
标题翻译：信息处理设备，信息处理方法，信息记录介质和程序
公开(公告)号：US20110210947A1
公开(公告)日：2011-09-01
申请号：US13121321
申请日：2009-10-01
申请人： Satoshi Kawaguchi , Yuji Takeuchi
发明人： Satoshi Kawaguchi , Yuji Takeuchi
IPC分类号： G06F3/042
CPC分类号： A63F13/42 , A63F13/04 , A63F13/10 , A63F13/2145 , A63F13/92 , A63F2300/1075 , A63F2300/1087 , A63F2300/204 , A63F2300/6045 , G06F3/0304 , G06F3/04847 , G06F3/0488 , G06F2203/04101
摘要： To provide an information processing apparatus having a user interface for enabling a user to readily give an instruction. A distance distribution image obtaining unit obtains a distance distribution image produced based a measured result output from a distance distribution measuring unit for measuring distance distribution to an object within a predetermined view field. An instruction content data producing unit produces instruction content data, based on the distance distribution image. An information processing execution unit obtains the instruction content data produced by the instruction content data producing unit, and carries out information processing based on the instruction content data.
摘要翻译：提供具有使用户能够容易地给出指令的用户界面的信息处理设备。距离分布图像获取单元根据距离分布测量单元输出的测量结果获得距离分布图像，用于测量在预定视场内的对象的距离分布。指示内容数据生成部基于距离分布图像生成指示内容数据。信息处理执行单元获取由指令内容数据产生单元产生的指令内容数据，并且执行基于指令内容数据的信息处理。

98. 发明授权

US07838404B2 Method of fabricating a nonvolatile semiconductor memory 有权
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US07838404B2
公开(公告)日：2010-11-23
申请号：US12543604
申请日：2009-08-19
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.
摘要翻译：一种非易失性半导体存储器制造方法，包括在半导体衬底上形成第一绝缘膜和浮栅电极材料; 通过蚀刻第一绝缘膜和浮栅电极材料分别形成栅绝缘膜和浮栅电极，并通过蚀刻半导体衬底形成用于元件隔离区的沟槽; 以及通过在所述沟槽中埋入第二绝缘膜并使所述第二绝缘膜平坦化来形成元件区域和所述元件隔离区域。

99. 发明授权

US07498630B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07498630B2
公开(公告)日：2009-03-03
申请号：US11559785
申请日：2006-11-14
申请人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
发明人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
摘要翻译：一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

100. 发明授权

US07449745B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
标题翻译：具有沟槽型元件隔离区域的非易失性半导体存储器件
公开(公告)号：US07449745B2
公开(公告)日：2008-11-11
申请号：US11687019
申请日：2007-03-16
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

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