专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08884924B2 Information processing apparatus, information processing method, information recording medium, and program 有权
标题翻译：信息处理装置，信息处理方法，信息记录介质和程序
公开(公告)号：US08884924B2
公开(公告)日：2014-11-11
申请号：US13121321
申请日：2009-10-01
申请人： Satoshi Kawaguchi , Yuji Takeuchi
发明人： Satoshi Kawaguchi , Yuji Takeuchi
IPC分类号： G06F3/042 , G06F3/0484 , A63F13/40 , G06F3/0488 , G06F3/03 , A63F13/219
CPC分类号： A63F13/42 , A63F13/04 , A63F13/10 , A63F13/2145 , A63F13/92 , A63F2300/1075 , A63F2300/1087 , A63F2300/204 , A63F2300/6045 , G06F3/0304 , G06F3/04847 , G06F3/0488 , G06F2203/04101
摘要： To provide an information processing apparatus having a user interface for enabling a user to readily give an instruction. A distance distribution image obtaining unit obtains a distance distribution image produced based a measured result output from a distance distribution measuring unit for measuring distance distribution to an object within a predetermined view field. An instruction content data producing unit produces instruction content data, based on the distance distribution image. An information processing execution unit obtains the instruction content data produced by the instruction content data producing unit, and carries out information processing based on the instruction content data.
摘要翻译：提供具有使用户能够容易地给出指令的用户界面的信息处理设备。距离分布图像获取单元根据距离分布测量单元输出的测量结果获得距离分布图像，用于测量在预定视场内的对象的距离分布。指示内容数据生成部基于距离分布图像生成指示内容数据。信息处理执行单元获取由指令内容数据产生单元产生的指令内容数据，并且执行基于指令内容数据的信息处理。

2. 发明申请

US20110210947A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION RECORDING MEDIUM, AND PROGRAM 有权
标题翻译：信息处理设备，信息处理方法，信息记录介质和程序
公开(公告)号：US20110210947A1
公开(公告)日：2011-09-01
申请号：US13121321
申请日：2009-10-01
申请人： Satoshi Kawaguchi , Yuji Takeuchi
发明人： Satoshi Kawaguchi , Yuji Takeuchi
IPC分类号： G06F3/042
CPC分类号： A63F13/42 , A63F13/04 , A63F13/10 , A63F13/2145 , A63F13/92 , A63F2300/1075 , A63F2300/1087 , A63F2300/204 , A63F2300/6045 , G06F3/0304 , G06F3/04847 , G06F3/0488 , G06F2203/04101
摘要： To provide an information processing apparatus having a user interface for enabling a user to readily give an instruction. A distance distribution image obtaining unit obtains a distance distribution image produced based a measured result output from a distance distribution measuring unit for measuring distance distribution to an object within a predetermined view field. An instruction content data producing unit produces instruction content data, based on the distance distribution image. An information processing execution unit obtains the instruction content data produced by the instruction content data producing unit, and carries out information processing based on the instruction content data.
摘要翻译：提供具有使用户能够容易地给出指令的用户界面的信息处理设备。距离分布图像获取单元根据距离分布测量单元输出的测量结果获得距离分布图像，用于测量在预定视场内的对象的距离分布。指示内容数据生成部基于距离分布图像生成指示内容数据。信息处理执行单元获取由指令内容数据产生单元产生的指令内容数据，并且执行基于指令内容数据的信息处理。

3. 发明申请

US20110186921A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20110186921A1
公开(公告)日：2011-08-04
申请号：US13085884
申请日：2011-04-13
申请人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

4. 发明授权

US07893477B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US07893477B2
公开(公告)日：2011-02-22
申请号：US11829320
申请日：2007-07-27
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

5. 发明申请

US20110010402A1 DATA-DRIVEN DATABASE PROCESSOR 有权
标题翻译：数据驱动数据库处理器
公开(公告)号：US20110010402A1
公开(公告)日：2011-01-13
申请号：US12812016
申请日：2008-12-24
申请人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
发明人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
IPC分类号： G06F7/00
CPC分类号： G06F17/3051 , G06F17/30371 , G06F17/30595
摘要： Provided is a technique for a data-driven database which frees a user from having to be conscious of a sequence in which instructions of a program for accessing a database are described, an interrelation of data items, and the like, and from having to describe redundant instructions. A data-driven database processor includes: schema definition storage means 2 for storing a schema definition of a database 24; derived definition storage means 3 for storing a derived definition describing a cause-and-effect relationship that exists when a value of a given data item is derived from a value of another data item; derived definition processing means 26 for generating a trigger program 27 that makes a chain of changes to values of data items based on the cause-and-effect relationship described in the derived definition; and a database management system 23 for executing the trigger program 27 when a change is made to the other data item that affects the value of the given data item.
摘要翻译：提供了一种用于数据驱动数据库的技术，其释放用户不必意识到描述用于访问数据库的程序的指令，数据项的相关性等的序列，并且不必描述冗余指令。数据驱动数据库处理器包括：用于存储数据库24的模式定义的模式定义存储装置2; 派生定义存储装置3，用于存储描述当从另一数据项的值导出给定数据项的值时存在的因果关系的派生定义; 导出定义处理装置26，用于基于导出的定义中描述的因果关系，产生触发程序27，触发程序27使数据项的值变化链; 以及数据库管理系统23，用于当对影响给定数据项的值的其他数据项进行改变时，执行触发程序27。

6. 发明授权

US07595522B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07595522B2
公开(公告)日：2009-09-29
申请号：US11565822
申请日：2006-12-01
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of the floating gate electrode; and a control gate electrode formed on the floating gate electrode via the inter-gate insulating film, wherein a portion from the upper surface of the floating gate electrode to at least a middle of the portion of the side surface which is covered with the inter-gate insulating film has a tapered shape largely inclined to a direction perpendicular to a surface of the semiconductor substrate, compared to the other portion of the side surface.
摘要翻译：根据本发明，提供了一种非易失性半导体存储器，其具有：形成在由半导体衬底上的元件隔离区域隔离的元件区域上的栅极绝缘膜上的浮栅电极; 形成为覆盖从所述浮栅电极的侧面的上表面到中间的部分的栅极间绝缘膜; 以及通过所述栅极间绝缘膜形成在所述浮栅上的控制栅电极，其中，从所述浮栅电极的上表面到所述侧表面的所述部分的至少中间的部分，与侧面的其他部分相比，栅极绝缘膜具有大致倾斜于垂直于半导体衬底的表面的方向的锥形形状。

7. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

8. 发明申请

US20080290396A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20080290396A1
公开(公告)日：2008-11-27
申请号：US12125546
申请日：2008-05-22
申请人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
发明人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.
摘要翻译：根据本发明的一个方面的半导体存储器包括半导体衬底，其包括存储单元阵列区域和与存储单元阵列区域相邻的互连线区域，设置在存储单元阵列区域中的存储单元，提供的接触插头以及控制栅极线，其设置为从互连线区域延伸到存储单元阵列区域，并将接触插头与存储器单元连接，其中设置在存储单元阵列中的控制栅极线区域包括金属硅化物，并且设置在互连线区域中的控制栅极线在互连线区域的任何部分不包括金属硅化物。

9. 发明授权

US07417281B2 Semiconductor device with a selection gate and a peripheral gate 有权
标题翻译：具有选择栅极和外围栅极的半导体器件
公开(公告)号：US07417281B2
公开(公告)日：2008-08-26
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

10. 发明申请

US20080119021A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080119021A1
公开(公告)日：2008-05-22
申请号：US12007751
申请日：2008-01-15
申请人： Yoshio Ozawa , Shigehiko Saida , Yuji Takeuchi , Masanobu Saito
发明人： Yoshio Ozawa , Shigehiko Saida , Yuji Takeuchi , Masanobu Saito
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括隧道绝缘膜，所述隧道绝缘膜具有在非易失性的沟道宽度方向周期性且连续变化的膜厚度存储单元，设置在隧道绝缘膜上的浮置栅电极，设置在浮置栅电极上方的控制栅电极，以及设置在控制栅电极和浮栅之间的电极间绝缘膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式