专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20090013231A1 Multi-bit error correction scheme in multi-level memory storage system 有权
标题翻译：多级存储系统中的多位纠错方案
公开(公告)号：US20090013231A1
公开(公告)日：2009-01-08
申请号：US11772347
申请日：2007-07-02
申请人： Chung H. Lam
发明人： Chung H. Lam
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C11/56 , G11C29/00
摘要： A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value.
摘要翻译：用于操作存储器单元集合的方法，系统和计算机软件产品。集合中的存储单元存储由特征参数的特征参数带分隔的二进制多位值。在一个实施例中，比较单元比较每个二进制多位值的检索计数和存储的计数。从存储单元集合中检索到与二进制多位值的出现次数相等的检索计数。存储的计数等于二进制多位值的出现次数存储在存储单元集合中。纠错单元然后将错误存储器单元分配给具有与所检索的二进制多位值相关联的特性参数带相邻的特征参数频带内的特性参数值的校正二进制多位值，使得检索到的计数每个二进制多位值的值等于每个二进制多位值的存储计数。

92. 发明申请

US20080277644A1 SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS 有权
标题翻译：使用可编程的开关阵列电路和系统，具有相变材料的结构
公开(公告)号：US20080277644A1
公开(公告)日：2008-11-13
申请号：US11745811
申请日：2007-05-08
申请人： Kuan-Neng Chen , Chung H. Lam
发明人： Kuan-Neng Chen , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1206 , H01L45/126 , H01L45/1286 , H01L45/144 , H01L45/148 , H03K19/1736
摘要： The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided.
摘要翻译：本发明提供至少一个可编程通孔结构，其包括直接接触加热元件的至少两个相变材料通孔，所述可编程通孔结构还包括与加热元件的第一部分接触的第一端子，第二与所述加热元件的第二部分接触的端子，与所述至少两个可编程通孔中的一个接触的第三端子以及与所述至少两个可编程通孔中的另一个接触的第四端子; 与所述第三和第四端子中的一个接触的第一电路块; 与不与第一电路块接触的第三或第四端子接触的第二电路块; 与所述第一和第二端子中的一个接触的第一场效应晶体管的源极区域; 以及与不与第一场效应晶体管的源极区域接触的第一或第二端子接触的第二场效应晶体管的漏极区域。还提供了一种操作至少一个可编程通孔结构的方法。

93. 发明申请

US20080251778A1 FOUR-TERMINAL PROGRAMMABLE VIA-CONTAINING STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译：四端可编程的通用结构及其制造方法
公开(公告)号：US20080251778A1
公开(公告)日：2008-10-16
申请号：US11733523
申请日：2007-04-10
申请人： Kuan-Neng Chen , Chung H. Lam
发明人： Kuan-Neng Chen , Chung H. Lam
IPC分类号： H01L47/00 , H01L21/44
CPC分类号： H01L45/148 , H01L23/525 , H01L45/06 , H01L45/1206 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L2924/0002 , Y10S438/90 , H01L2924/00
摘要： A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.
摘要翻译：一种半导体结构，其包括两个可编程通孔，每个可编程通孔包含与加热材料集成的相变材料。特别地，本发明提供一种结构，其中每个包含相变材料的两个可编程通孔位于加热材料的相对表面上。加热材料的上表面的每个端部连接到金属端子。与加热材料的上表面的端部接触的这些金属端子可以各自连接到控制和切换两个可编程通孔的电阻状态的外部部件。本发明结构的两个可编程通孔各自连接到另一金属端子。与可编程通孔相关联的这些金属端子也可以连接到可能存在于结构中的电路块。

94. 发明授权

US07256415B2 Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells 有权
标题翻译：存储器件以及通过同时调节多个存储单元中的过渡金属氧化物层来制造器件的方法
公开(公告)号：US07256415B2
公开(公告)日：2007-08-14
申请号：US11140780
申请日：2005-05-31
申请人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung H. Lam , Gerhard I. Meijer
发明人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung H. Lam , Gerhard I. Meijer
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
摘要翻译：公开了包含一系列单个或双重存储器单元的非易失性存储器件。单个存储器单元基本上是“U”形的。双重存储单元包括两个基本上“U”形的存储单元。每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

95. 发明授权

US07057923B2 Field emission phase change diode memory 失效
标题翻译：场发射相变二极管存储器
公开(公告)号：US07057923B2
公开(公告)日：2006-06-06
申请号：US10732582
申请日：2003-12-10
申请人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
发明人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
IPC分类号： G11C11/00 , H01L27/00 , H01L21/00
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer. The apex may penetrate the GST layer
摘要翻译：可以是存储单元的存储单元和包括存储单元的阵列的集成电路（IC）芯片和形成IC的方法。每个存储单元形成在顶部底部电极之间。每个电池包括可以是硫族化物，特别是锗（Ge），锑（Sb），碲（Te）或GST层的相变层。电池还包括一个触笔，触笔的顶点与GST层接触。顶点可以穿透GST层

96. 发明授权

US06344373B1 Antifuse structure and process 失效
标题翻译：形成反熔丝的方法
公开(公告)号：US06344373B1
公开(公告)日：2002-02-05
申请号：US09106980
申请日：1998-06-29
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

97. 发明授权

US5811870A Antifuse structure 失效
标题翻译：防腐结构
公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

98. 发明授权

US5545583A Method of making semiconductor trench capacitor cell having a buried strap 失效
标题翻译：制造具有掩埋带的半导体沟槽电容器电池的方法
公开(公告)号：US5545583A
公开(公告)日：1996-08-13
申请号：US421115
申请日：1995-04-13
申请人： Chung H. Lam , David K. Lord , Judith A. Wright
发明人： Chung H. Lam , David K. Lord , Judith A. Wright
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10861 , H01L29/66181 , H01L29/945
摘要： A semiconductor trench capacitor structure having a first level aligned insulation structure and buried strap that extends from within the trench into the semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench extending into both the trench capacitor and the semiconductor substrate, depositing and densifying an insulating material within the shallow trench and using a resist layer to define and etch a strap trench aligned with the wall of the shallow trench, depositing a layer of conductive material within the strap trench and followed by depositing an insulating material therein.
摘要翻译：一种半导体沟槽电容器结构，其具有从沟槽内延伸到半导体衬底中的第一级对准绝缘结构和埋入带。半导体沟槽电容器结构可以通过形成延伸到沟槽电容器和半导体衬底中的浅沟槽，在浅沟槽内沉积和致密绝缘材料并使用抗蚀剂层来限定和蚀刻与壁对准的带沟槽来制造的浅沟槽，在带状沟槽内沉积导电材料层，然后在其中沉积绝缘材料。

99. 发明授权

US5291439A Semiconductor memory cell and memory array with inversion layer 失效
标题翻译：半导体存储单元和具有反转层的存储器阵列
公开(公告)号：US5291439A
公开(公告)日：1994-03-01
申请号：US758656
申请日：1991-09-12
申请人： Bruce A. Kauffmann , Chung H. Lam , Jerome B. Lasky
发明人： Bruce A. Kauffmann , Chung H. Lam , Jerome B. Lasky
IPC分类号： G11C17/00 , B82B1/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L27/115
摘要： A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.
摘要翻译：适用于电可擦除可编程只读存储器（EEPROM）的存储单元包括直接写单元能力。存储单元制造在衬底上，并使用设置在衬底上方的反相源栅极来在其中产生耗尽源。耗尽源限定衬底中具有相关漏极的沟道区。电隔离的浮置栅极设置在衬底上方以便与衬底沟道区域的至少一部分重叠。此外，编程门被设置为与浮置栅极的一部分重叠，并且还提供了至少部分地在衬底沟道区域上对准的存取栅，使得限定了双栅极器件。也可以构造这样的存储单元阵列。

100. 发明授权

US5268330A Process for improving sheet resistance of an integrated circuit device gate 失效
标题翻译：用于提高集成电路器件栅极的薄层电阻的工艺
公开(公告)号：US5268330A
公开(公告)日：1993-12-07
申请号：US989604
申请日：1992-12-11
申请人： John H. Givens , James S. Nakos , Peter A. Burke , Craig M. Hill , Chung H. Lam
发明人： John H. Givens , James S. Nakos , Peter A. Burke , Craig M. Hill , Chung H. Lam
IPC分类号： H01L21/28 , H01L21/321 , H01L21/336 , H01L21/768 , H01L29/78 , H01L21/283 , H01L21/302
CPC分类号： H01L21/321 , H01L21/76802 , Y10S438/934
摘要： A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式