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91. 发明授权

US07233523B2 Optimized layout for multi-bit memory banks each with two data latches and two arithmetic circuits 有权
标题翻译：多位存储库的优化布局，每个存储库都有两个数据锁存器和两个运算电路
公开(公告)号：US07233523B2
公开(公告)日：2007-06-19
申请号：US10503619
申请日：2002-02-28
申请人： Tsutomu Nakajima , Keiichi Yoshida
发明人： Tsutomu Nakajima , Keiichi Yoshida
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , G11C11/5642 , G11C16/26
摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.
摘要翻译：基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。例如，在存储体2a的左侧，沿着存储体2a的一个短边设置数据锁存器6a，而在右侧，沿着另一个短边设置数据锁存器6b，银行2 a。在数据锁存器6a，6b的下侧设有运算电路7a，7b。数据锁存器6a，6b分别由SRAM形成。感测锁定器5a相对于感测闩锁行的中心在左右方向上被分成一半。划分的检测锁存器5a通过分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b连接。

92. 发明授权

US07209698B2 Method and apparatus for image forming capable of using minuscule spherical particles of toner, a process cartridge in use for the apparatus and a toner used in the image forming for obtaining an image with a high thin line reproducibility 有权
标题翻译：用于图像形成的方法和装置，其能够使用调色剂的微小球形颗粒，用于该装置的处理盒和用于图像形成的调色剂，以获得具有高细线再现性的图像
公开(公告)号：US07209698B2
公开(公告)日：2007-04-24
申请号：US10922963
申请日：2004-08-23
申请人： Takaaki Tawada , Shinichi Kawahara , Takeo Suda , Chohtaroh Kataoka , Keiichi Yoshida , Haruji Mizuishi
发明人： Takaaki Tawada , Shinichi Kawahara , Takeo Suda , Chohtaroh Kataoka , Keiichi Yoshida , Haruji Mizuishi
IPC分类号： G03G21/00
CPC分类号： G03G9/0823 , G03G9/0804 , G03G9/0827 , G03G9/08755 , G03G15/0258 , G03G21/00 , G03G21/0005 , G03G2215/021 , G03G2221/0084
摘要： An image forming apparatus includes an image bearing member configured to bear a toner image on a surface thereof. A charging mechanism is configured to uniformly charge the surface of the image bearing member. An intermediate transfer mechanism is configured to transfer the toner image from the image bearing member onto an image receiver. A cleaning mechanism is configured to clean the surface of the image bearing member after the toner image is transferred onto the image receiver. A lubricant supplying mechanism is configured to supply a lubricant contained therein onto the surface of the image bearing member and form a thin layer using a lubricating blade. The lubricant supplying mechanism is disposed between the cleaning mechanism and the charging mechanism.
摘要翻译：图像形成装置包括被构造成在其表面上承载调色剂图像的图像承载部件。充电机构构造成对图像承载部件的表面均匀充电。中间转印机构构造成将调色剂图像从图像承载部件转印到图像接收器上。清洁机构构造成在将调色剂图像转印到图像接收器上之后清洁图像承载部件的表面。润滑剂供给机构被构造成将容纳在其中的润滑剂供给到图像承载部件的表面上，并使用润滑叶片形成薄层。润滑剂供给机构设置在清洁机构和充电机构之间。

93. 发明申请

US20070081832A1 Image forming apparatus having a developer conveying system and associated methodology 有权
标题翻译：具有显影剂输送系统和相关方法的图像形成装置
公开(公告)号：US20070081832A1
公开(公告)日：2007-04-12
申请号：US11543830
申请日：2006-10-06
申请人： Keiichi Yoshida , Yoshio Hattori , Shinichi Kawahara , Takatsugu Fujishiro , Shuji Tanaka
发明人： Keiichi Yoshida , Yoshio Hattori , Shinichi Kawahara , Takatsugu Fujishiro , Shuji Tanaka
IPC分类号： G03G15/08
CPC分类号： G03G15/0822 , G03G2215/0822 , G03G2215/0827
摘要： An image forming apparatus includes an image carrier configured to form a latent image and a development unit including a development member configured to develop the latent image forming on the image carrier with a developer, and a plurality of conveying members each including at least one spiral vane and configured to rotate around a spiral axis of the spiral vane to revolve and transfer the developer around the spiral axis in a direction along the spiral axis, the plurality of conveying members configured to transfer the developer sequentially from a conveying member to an adjacent conveying member and including a first conveying member arranged at a position closest to the development member to supply developer to the development member, wherein a number of the spiral vanes of the first conveying member are at least two and is also greater than the number of spiral vanes in the remaining conveying members.
摘要翻译：图像形成装置包括被构造成形成潜像的图像载体和显影单元，显影单元包括显影部件，显影部件被构造成用显影剂显影在图像载体上形成的潜像，以及多个输送部件，每个输送部件包括至少一个螺旋叶片并且构造成围绕所述螺旋叶片的螺旋轴线旋转，以沿着所述螺旋轴线的方向围绕所述螺旋轴线旋转和传送所述显影剂，所述多个输送构件被构造成将所述显影剂从输送构件依次传送到相邻的输送构件并且包括布置在最靠近显影构件的位置处以将显影剂供应到显影构件的第一输送构件，其中第一输送构件的多个螺旋叶片为至少两个并且还大于螺旋叶片的数量剩余的输送构件。

94. 发明授权

US07002848B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07002848B2
公开(公告)日：2006-02-21
申请号：US10505952
申请日：2002-02-28
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Michitaro Kanamitsu
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Michitaro Kanamitsu
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/24
摘要： This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.
摘要翻译：这是一种非易失性半导体存储器件，其能够以1倍锁存电路+ 2xSRAM配置提高Y个存取电路的写入操作速度。在多值闪速存储器中，在从低电压侧进行写入的情况下，在数据从SRAM向“10”，“00”分布的感测锁存电路进行数据的写入和不稳定判定之后，在“01”分发数据传输之后，写入完成; 在数据传输“11”分配字干扰确定完成后; 并且在该顺序中进行简化的上限确定。特别是通过（1）从多值存储器中的阈值电压分布的低电压侧写入，以及（2）在每个阈值电压分布之后连续施加“写入处理”和“上限确定处理” 对于“10”和“00”分配的写入处理，由于所有存储单元的阈值电压都低于“10”和“00”分布的上限确定电压，所以上层不需要写入数据传输因为其他阈值电压分布未被屏蔽，所以限制确定处理。

95. 发明申请

US20050237803A1 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US20050237803A1
公开(公告)日：2005-10-27
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

96. 发明申请

US20050228962A1 Non-volatile storage device 有权
标题翻译：非易失性存储设备
公开(公告)号：US20050228962A1
公开(公告)日：2005-10-13
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F13/00 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

97. 发明申请

US20050095769A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050095769A1
公开(公告)日：2005-05-05
申请号：US10499667
申请日：2002-02-28
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C16/04 , G11C16/24 , G11C16/34 , H01L21/8238
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

98. 发明申请

US20050082579A1 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050082579A1
公开(公告)日：2005-04-21
申请号：US10503640
申请日：2002-02-28
申请人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
发明人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
IPC分类号： G11C16/20 , G11C16/26 , H01L29/768
CPC分类号： G11C16/26 , G11C16/20
摘要： The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.
摘要翻译：所公开的闪存具有多数逻辑电路3和移位寄存器6 1至6 3 3。三个存储体中的三个存储器分别包括管理信息区域KAs以存储包括电源修剪数据和位线恢复数据的二进制管理信息。在闪速存储器的初始化期间，多数逻辑电路3对从管理信息区域Ka检索的管理信息比特进行纠错，并将该信息输出到修整/恢复数据缓冲器11，从而非常快速地提供高度可靠的管理信息。移位寄存器6 1〜6 3将从控制电路12输出的控制信号延迟一定时间，然后将控制信号输出到读出放大器42〜 44。该延迟使得可以使存储体2a至2d的工作电流在不同时间开始流动并且抑制在闪速存储器中流动的峰值电流。

99. 发明授权

US06775185B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06775185B2
公开(公告)日：2004-08-10
申请号：US10404085
申请日：2003-04-02
申请人： Tomoyuki Fujisawa , Keiichi Yoshida , Yoshinori Takase , Takashi Horii
发明人： Tomoyuki Fujisawa , Keiichi Yoshida , Yoshinori Takase , Takashi Horii
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1042 , G11C7/1051 , G11C7/106 , G11C16/10 , G11C16/26
摘要： A memory bank comprises nonvolatile memory sections and two buffer sections to respectively store information of access unit of the nonvolatile memory sections. In response to the instruction of access operation, the memory bank performs data transfer between one buffer section of the memory bank and the nonvolatile memory section. In parallel to this data transfer, the memory bank also enables control of interleave operation to perform data transfer between the other buffer section of the relevant memory bank and the external side. Accordingly, high speed access can be realized by conducting in parallel the data transfer between the nonvolatile memory section and the buffer section and data transfer between the buffer section and the external side in the interleave operation. Moreover, high speed write and read access to the nonvolatile memory section can also be realized.
摘要翻译：存储体包括非易失性存储器部分和两个缓冲器部分，用于分别存储非易失性存储器部分的存取单元的信息。响应于访问操作的指令，存储体在存储体的一个缓冲区和非易失性存储部之间执行数据传送。与该数据传输并行，存储体还能够进行交织操作的控制，以在相关存储体的另一个缓冲区和外部侧之间执行数据传送。因此，可以通过并行地进行非易失性存储器部分和缓冲器部分之间的数据传输以及在交错操作中的缓冲器部分和外部侧之间的数据传送来实现高速访问。此外，还可以实现对非易失性存储器部分的高速写入和读取访问。

100. 发明授权

US06496418B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06496418B2
公开(公告)日：2002-12-17
申请号：US09985188
申请日：2001-11-01
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

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