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1. 发明授权

US07334080B2 Nonvolatile memory with independent access capability to associated buffer 有权
标题翻译：非易失性存储器，具有对相关缓冲区的独立访问能力
公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

2. 发明申请

US20050228962A1 Non-volatile storage device 有权
标题翻译：非易失性存储设备
公开(公告)号：US20050228962A1
公开(公告)日：2005-10-13
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F13/00 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

3. 发明申请

US20050082579A1 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050082579A1
公开(公告)日：2005-04-21
申请号：US10503640
申请日：2002-02-28
申请人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
发明人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
IPC分类号： G11C16/20 , G11C16/26 , H01L29/768
CPC分类号： G11C16/26 , G11C16/20
摘要： The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.
摘要翻译：所公开的闪存具有多数逻辑电路3和移位寄存器6 1至6 3 3。三个存储体中的三个存储器分别包括管理信息区域KAs以存储包括电源修剪数据和位线恢复数据的二进制管理信息。在闪速存储器的初始化期间，多数逻辑电路3对从管理信息区域Ka检索的管理信息比特进行纠错，并将该信息输出到修整/恢复数据缓冲器11，从而非常快速地提供高度可靠的管理信息。移位寄存器6 1〜6 3将从控制电路12输出的控制信号延迟一定时间，然后将控制信号输出到读出放大器42〜 44。该延迟使得可以使存储体2a至2d的工作电流在不同时间开始流动并且抑制在闪速存储器中流动的峰值电流。

4. 发明申请

US20080098190A1 NON-VOLATILE STORAGE DEVICE 有权
标题翻译：非易失存储器件
公开(公告)号：US20080098190A1
公开(公告)日：2008-04-24
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

5. 发明授权

US07085189B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07085189B2
公开(公告)日：2006-08-01
申请号：US10503640
申请日：2002-02-28
申请人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
发明人： Takashi Horii , Ken Matsubara , Keiichi Yoshida
IPC分类号： G11C8/00
CPC分类号： G11C16/26 , G11C16/20
摘要： The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.
摘要翻译：所公开的闪存具有多数逻辑电路3和移位寄存器6 1至6 3 3。三个存储体中的三个存储器分别包括管理信息区域KAs以存储包括电源修剪数据和位线恢复数据的二进制管理信息。在闪速存储器的初始化期间，多数逻辑电路3对从管理信息区域Ka检索的管理信息比特进行纠错，并将该信息输出到修整/恢复数据缓冲器11，从而非常快速地提供高度可靠的管理信息。移位寄存器6 1〜6 3将从控制电路12输出的控制信号延迟某一时间段，然后将控制信号输出到读出放大器4 < SUB> 2 4 <4>。该延迟使得可以使存储体2a至2d的工作电流在不同时间开始流动并且抑制在闪速存储器中流动的峰值电流。

6. 发明授权

US07581058B2 Non-volatile memory having multiple erase operations 有权
标题翻译：具有多次擦除操作的非易失性存储器
公开(公告)号：US07581058B2
公开(公告)日：2009-08-25
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

7. 发明授权

US07095657B2 Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
标题翻译：能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件
公开(公告)号：US07095657B2
公开(公告)日：2006-08-22
申请号：US11224964
申请日：2005-09-14
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C7/10
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

8. 发明授权

US06958940B2 Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
标题翻译：能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件
公开(公告)号：US06958940B2
公开(公告)日：2005-10-25
申请号：US10499667
申请日：2002-02-28
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C16/04 , G11C16/24 , G11C16/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

9. 发明申请

US20050095769A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050095769A1
公开(公告)日：2005-05-05
申请号：US10499667
申请日：2002-02-28
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C16/04 , G11C16/24 , G11C16/34 , H01L21/8238
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

10. 发明申请

US20060007737A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060007737A1
公开(公告)日：2006-01-12
申请号：US11224964
申请日：2005-09-14
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

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