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91. 发明授权

US06794249B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06794249B2
公开(公告)日：2004-09-21
申请号：US10378101
申请日：2003-02-28
申请人： Herbert Palm , Josef Willer
发明人： Herbert Palm , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.
摘要翻译：导电层或层序列优选地包括施加到金属硅化物或多晶硅层的含金属层以降低掩埋位线的电阻。层或层序列已经以带状形式图案化，以对应于位线，并且布置在具有ONO存储层序列的存储晶体管的源极/漏极区域和布置在沟槽中的栅极电极。金属硅化物优选为硅化钴，并且含金属层优选为硅化钨或WN / W。

92. 发明授权

US06646299B2 Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration 有权
公开(公告)号：US06646299B2
公开(公告)日：2003-11-11
申请号：US10126365
申请日：2002-04-19
申请人： Josef Willer , Christofer Hierold
发明人： Josef Willer , Christofer Hierold
IPC分类号： H01L2708
CPC分类号： H01L28/92 , H01L28/55
摘要： A first capacitor electrode and at least part of a second capacitor electrode of a capacitor are produced in depressions of an auxiliary layer by electroplating. The auxiliary layer is then removed and at least partially replaced by a capacitor dielectric. The first capacitor electrode and the part of the second capacitor electrode may be composed of a metal, for example platinum. The capacitor dielectric can be composed, for example, of barium-strontium-titanate.

93. 发明授权

US06639269B1 Electrically programmable memory cell configuration and method for fabricating it 失效
标题翻译：电可编程存储单元配置及其制造方法
公开(公告)号：US06639269B1
公开(公告)日：2003-10-28
申请号：US09648952
申请日：2000-08-25
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11546 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric disposed on sidewalls of the depression. Since the floating gate electrode has a larger area than the channel region, a capacitance formed by a control gate electrode applied on the floating gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region. Two source/drain regions of the transistor likewise adjoin the sidewalls of the depression. An insulation, which is thicker than the first dielectric, isolates the floating gate electrode from the source/drain regions, so that the source/drain regions do not contribute to the coupling ratio.
摘要翻译：存储单元包含平面晶体管，其沟道区设置在衬底中的凹陷的底部。晶体管的浮置栅电极邻接凹陷的底部，底部设置有设置在凹陷的侧壁上的第一电介质。由于浮栅电极具有比沟道区更大的面积，所以由施加在浮置栅电极和浮置栅电极上的控制栅电极形成的电容大于由浮栅电极和沟道区形成的电容。晶体管的两个源极/漏极区同样邻接凹陷的侧壁。比第一电介质厚的绝缘体将浮置栅极与源极/漏极区隔离，使得源极/漏极区域对耦合比没有贡献。

94. 发明授权

US06475866B2 Method for production of a memory cell arrangement 失效
标题翻译：存储单元布置的制造方法
公开(公告)号：US06475866B2
公开(公告)日：2002-11-05
申请号：US09774316
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

95. 发明授权

US06445046B1 Memory cell arrangement and process for manufacturing the same 失效
标题翻译：存储单元布置及其制造方法
公开(公告)号：US06445046B1
公开(公告)日：2002-09-03
申请号：US09331034
申请日：1999-06-15
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
IPC分类号： H01L29772
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
摘要翻译：多个彼此绝缘的存储器单元线路，并且分别包括第一掺杂区域和第二掺杂区域，在该第二掺杂区域和第二掺杂区域之间包含具有电荷载流子阱的材料和多个栅电极的栅极电介质。相邻栅电极的间隔小于栅电极的尺寸。通过将电荷载体引入栅极电介质来存储信息。优选地，通过间隔物技术来制造栅电极。

96. 发明授权

US06365888B2 Method for capacitive image acquisition 失效
标题翻译：电容式图像采集方法
公开(公告)号：US06365888B2
公开(公告)日：2002-04-02
申请号：US09782733
申请日：2001-02-13
申请人： Paul-Werner Von Basse , Josef Willer , Thomas Scheiter , Stephan Marksteiner
发明人： Paul-Werner Von Basse , Josef Willer , Thomas Scheiter , Stephan Marksteiner
IPC分类号： H01L2700
CPC分类号： G06K9/0002
摘要： A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.
摘要翻译：导体区域的格子阵列用于电容图像采集。每个壳体中的屏蔽导体都设置在用于测量的导体之间。在多个充电和放电循环期间，为了防止屏蔽电容器之间的位移电流，电势总是沿着属于相应像素的导体承载。作为示例，具有反馈运算放大器的补偿线可以用于相同地改变导体上的电位。

97. 发明授权

US06265748B1 Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement 失效
标题翻译：垂直MOS晶体管根据存储的数据具有至少三个不同阈值电压的存储单元布置，以及制造所述布置的方法
公开(公告)号：US06265748B1
公开(公告)日：2001-07-24
申请号：US09180129
申请日：1998-11-02
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L2976
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种存储单元布置及其制造方法，其包括作为存储单元的垂直MOS晶体管，其中通过多级编程通过晶体管的至少三个不同的阈值电压值来存储信息。通过厚氧化物晶体管的栅极电介质的厚度获得一个阈值电压值，并且通过不同的沟道掺杂获得其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

98. 发明授权

US06242319B1 Method for fabricating an integrated circuit configuration 失效
标题翻译：制造集成电路结构的方法
公开(公告)号：US06242319B1
公开(公告)日：2001-06-05
申请号：US09498530
申请日：2000-02-04
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L2176
CPC分类号： H01L27/10858 , H01L23/544 , H01L25/50 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A first structure of a circuit configuration and a first alignment structure are produced in the region of a surface of a first substrate. The first alignment structure scatters electron beams differently than its surroundings. A second substrate, which is more transmissive to electron beams than the first alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align a mask with respect to the first structure, a position of the first alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an uncovered upper surface of the second substrate. The first structure may be a metallic line encapsulated by insulating material. A contact may connect the first structure to the second structure. With the aid of electron beam lithography, at least one second alignment structure may be produced in the region of the upper surface of the second substrate, using which the mask is aligned.
摘要翻译：在第一基板的表面的区域中制造电路结构和第一对准结构的第一结构。第一对准结构与其周围环境不同地散射电子束。与第一对准结构相比，对电子束更透射的第二衬底以这样的方式连接到第一衬底，使得第二衬底设置在第一衬底的表面之上。为了使掩模相对于第一结构对准，借助于电子束来确定第一对准结构的位置。借助于掩模，在第二基板的未覆盖的上表面的区域中产生电路构造的至少一个第二结构。第一结构可以是由绝缘材料包封的金属线。触点可以将第一结构连接到第二结构。借助于电子束光刻技术，可以在第二衬底的上表面的区域中产生至少一个第二对准结构，使用掩模进行对准。

99. 发明授权

US6165835A Method for producing a silicon capacitor 失效
标题翻译：硅电容器的制造方法
公开(公告)号：US6165835A
公开(公告)日：2000-12-26
申请号：US341937
申请日：1999-07-20
申请人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
发明人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10861 , H01L29/66181 , Y10S438/96
摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.
摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质层（4）和导电层（5），而不填充孔结构（2）。为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面压缩机械应力。

100. 发明授权

US5347696A Method for manufacturing a multi-layer capacitor 失效
标题翻译：多层电容器的制造方法
公开(公告)号：US5347696A
公开(公告)日：1994-09-20
申请号：US164719
申请日：1993-12-10
申请人： Josef Willer , Hermann Wendt , Hans Reisinger
发明人： Josef Willer , Hermann Wendt , Hans Reisinger
IPC分类号： C23F4/00 , H01G4/30 , H01L21/822 , H01L27/04 , H01G4/10
CPC分类号： H01G4/306 , Y10T29/435
摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).
摘要翻译：为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层（2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

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