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91. 发明授权

US07498640B2 Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby 失效
公开(公告)号：US07498640B2
公开(公告)日：2009-03-03
申请号：US10437930
申请日：2003-05-15
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

92. 发明授权

US07442612B2 Nitride-encapsulated FET (NNCFET) 有权
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07442612B2
公开(公告)日：2008-10-28
申请号：US11481532
申请日：2006-07-06
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

93. 发明申请

US20080254594A1 STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS 失效
标题翻译：应变硅CMOS混合晶体取向
公开(公告)号：US20080254594A1
公开(公告)日：2008-10-16
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/30
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

94. 发明授权

US07378336B2 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US07378336B2
公开(公告)日：2008-05-27
申请号：US11124978
申请日：2005-05-09
申请人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
发明人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

95. 发明授权

US07217949B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07217949B2
公开(公告)日：2007-05-15
申请号：US10883443
申请日：2004-07-01
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L29/06
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

96. 发明授权

US07071103B2 Chemical treatment to retard diffusion in a semiconductor overlayer 失效
标题翻译：化学处理以延缓半导体覆层中的扩散
公开(公告)号：US07071103B2
公开(公告)日：2006-07-04
申请号：US10710737
申请日：2004-07-30
申请人： Kevin K. Chan , Huajie Chen , Michael A. Gribelyuk , Judson R. Holt , Woo-Hyeong Lee , Ryan M. Mitchell , Renee T. Mo , Dan M. Mocuta , Werner A. Rausch , Paul A. Ronsheim , Henry K. Utomo
发明人： Kevin K. Chan , Huajie Chen , Michael A. Gribelyuk , Judson R. Holt , Woo-Hyeong Lee , Ryan M. Mitchell , Renee T. Mo , Dan M. Mocuta , Werner A. Rausch , Paul A. Ronsheim , Henry K. Utomo
IPC分类号： H01L21/44
CPC分类号： H01L21/28044 , H01L21/324
摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.
摘要翻译：本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

97. 发明授权

US07037798B2 Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
标题翻译：双极晶体管结构具有自对准引出的外在基极和方法
公开(公告)号：US07037798B2
公开(公告)日：2006-05-02
申请号：US10904482
申请日：2004-11-12
申请人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
发明人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译：本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加。该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。本发明还包括所得到的双极晶体管结构。

98. 发明授权

US06927454B2 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US06927454B2
公开(公告)日：2005-08-09
申请号：US10680820
申请日：2003-10-07
申请人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
发明人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

99. 发明授权

US06809005B2 Method to fill deep trench structures with void-free polysilicon or silicon 失效
标题翻译：用无孔多晶硅或硅填充深沟槽结构的方法
公开(公告)号：US06809005B2
公开(公告)日：2004-10-26
申请号：US10386880
申请日：2003-03-12
申请人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
发明人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/0237 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/763 , H01L29/66181
摘要： The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
摘要翻译：本发明提供了在其中制造基本上无空隙填料的沟槽结构的方法。填料可以从诸如沿沟槽的侧壁形成的多晶硅的衬垫材料生长。先前形成的空隙可以通过暴露空隙和生长外延硅来治愈。

100. 发明授权

US06759710B2 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06759710B2
公开(公告)日：2004-07-06
申请号：US10051562
申请日：2002-01-18
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L2976
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

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