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91. 发明授权

US06907502B2 Method for moving snoop pushes to the front of a request queue 失效
标题翻译：将snoop移动到请求队列前端的方法
公开(公告)号：US06907502B2
公开(公告)日：2005-06-14
申请号：US10264169
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.
摘要翻译：一种用于将窥探优先级的方法推送到在请求FIFO内调度请求的数据处理系统中。接收到的每个新请求被置于请求FIFO的最后位置，并且请求FIFO通常仅基于请求FIFO内的顺序授予请求。由于先前请求被顺序授权，所以随后的请求更接近请求FIFO的第一位置。然而，当在请求FIFO处接收到窥探推送时，窥探推送将自动插入请求FIFO的第一个位置，而在请求FIFO之前尚未被授予请求。

92. 发明授权

US06807608B2 Multiprocessor environment supporting variable-sized coherency transactions 失效
标题翻译：多处理器环境支持可变大小的一致性事务
公开(公告)号：US06807608B2
公开(公告)日：2004-10-19
申请号：US10077560
申请日：2002-02-15
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.
摘要翻译：用于执行可变大小的存储器一致性事务的方法和系统。耦合在从机和主机之间的总线接口单元可以被配置为从主机接收包括多个相干性颗粒的请求（主请求）。系统中的每个窥探单元可以被配置为一次窥探主请求中的不同数量的一致性粒子。一旦总线接口单元已经从每个窥探逻辑单元接收到指示集合的指示集合，指示主请求中的相关性集合的集合已被每个监听单元窥探，并且用于收集相关性颗粒的地址上的数据被侦听未被更新，总线接口单元可以允许未更新的那些一致性粒度的地址上的数据在请求主机和从机之间传送。

93. 发明授权

US5862353A Systems and methods for dynamically controlling a bus 失效
标题翻译：用于动态控制总线的系统和方法
公开(公告)号：US5862353A
公开(公告)日：1999-01-19
申请号：US823736
申请日：1997-03-25
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/362 , G06F13/364 , G06F13/372 , G06F13/36
CPC分类号： G06F13/364
摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in bus usage. Devices submit a priority level along with a bus request to a bus controller. Upon receiving multiple requests, an arbiter of the bus controller compares the priority levels associated with the different bus requests and grants control of the bus to the device having the highest priority level. During each cycle that a device has control of the bus, a feedback logic circuit of the bus controller determines whether other bus requests are pending, and if so, determines the highest pending request priority level. Signals corresponding to the results of these determinations are fed back to each device. The device having control of the bus uses the combination of the currently pending request priority level and the device's own latency timer to determine whether it should maintain control of the bus or relinquish control of the bus.
摘要翻译：具有访问公共共享总线的多个设备的计算机系统中的总线性能可以通过增加吞吐量和减少等待时间来改善，同时考虑总线使用的动态变化。设备将总线请求提交给总线控制器。在接收到多个请求时，总线控制器的仲裁器比较与不同总线请求相关联的优先级，并将总线的控制授权给具有最高优先级的设备。在每个周期中，器件具有对总线的控制，总线控制器的反馈逻辑电路确定其他总线请求是否正在等待，如果是，则确定最高待机请求优先级。与这些测定结果相对应的信号被反馈给每个设备。具有总线控制的设备使用当前挂起的请求优先级和设备自身的延迟定时器的组合来确定其是否应该保持对总线的控制或放弃对总线的控制。

94. 发明授权

US5724572A Method and apparatus for processing null terminated character strings 失效
标题翻译：处理空终止字符串的方法和装置
公开(公告)号：US5724572A
公开(公告)日：1998-03-03
申请号：US341789
申请日：1994-11-18
申请人： James N. Dieffenderfer , Harry I. Linzer , Thomas Andrew Sartorius
发明人： James N. Dieffenderfer , Harry I. Linzer , Thomas Andrew Sartorius
IPC分类号： G06F7/74 , G06F7/10
CPC分类号： G06F7/74 , Y10S707/99936
摘要： A method and apparatus for detecting the null byte at the end of a character string. The method and apparatus first logically concatenates two 32-bit input values into a single 64 bit value. Next, the 64-bit value is divided into 8 bytes. Then, a logical OR operation is performed on each byte and the results are put into an encoder. Finally, the encoder interprets the results of the OR operations and places output values into processor registers which indicate whether or where a null byte was detected.
摘要翻译：一种用于检测字符串末尾的空字节的方法和装置。该方法和设备首先将两个32位输入值逻辑级联为单个64位值。接下来，64位值被分为8个字节。然后，对每个字节执行逻辑或运算，并将结果放入编码器。最后，编码器解释OR操作的结果，并将输出值放在处理器寄存器中，指示是否检测到空字节。

95. 发明授权

US08943300B2 Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information 有权
标题翻译：用于使用预解码信息生成隐式和显式子程序调用返回地址预测的方法和装置
公开(公告)号：US08943300B2
公开(公告)日：2015-01-27
申请号：US12183086
申请日：2008-07-31
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/42 , G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3844 , G06F9/3005 , G06F9/30058 , G06F9/30101 , G06F9/322 , G06F9/3806
摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
摘要翻译：公开了一种用于模拟显式子程序调用的分支预测行为的装置。该装置包括被配置为接收指令地址和第二输入的第一输入。第二输入被配置为接收描述与子程序的隐式子程序调用有关的指令地址的预解码信息。响应于预解码信息，该装置还包括加法器，其被配置为向定义返回地址的指令地址添加常数，使得将返回地址存储到显式子例程资源，从而便于后续分支预测返回呼叫指令。

96. 发明申请

US20140006752A1 Qualifying Software Branch-Target Hints with Hardware-Based Predictions 审中-公开
标题翻译：合格软件分支 - 基于硬件预测的目标提示
公开(公告)号：US20140006752A1
公开(公告)日：2014-01-02
申请号：US13534649
申请日：2012-06-27
申请人： Michael William Morrow , James Norris Dieffenderfer , Thomas Andrew Sartorius , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
发明人： Michael William Morrow , James Norris Dieffenderfer , Thomas Andrew Sartorius , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
IPC分类号： G06F9/40
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.
摘要翻译：一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目的分支目标地址高速缓存，其中条目包括用于存储指令地址的标签字段，存储目标地址的目标字段，以及状态字段来存储状态值。在解码间接分支指令时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接分支指令的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目中的状态值，处理器将使用所存储的目标地址作为解码的间接分支指令的预测目标地址，或者将使用提供的软件提供的目标地址提示（如果可用）。

97. 发明授权

US08352682B2 Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system 有权
标题翻译：在弱排序存储系统中发出存储障碍命令的方法和装置
公开(公告)号：US08352682B2
公开(公告)日：2013-01-08
申请号：US12471652
申请日：2009-05-26
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F12/0811 , G06F12/0835
摘要： Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.
摘要翻译：描述了有效的技术来实现存储器访问的顺序。从未被配置为生成存储器障碍命令的设备接收到存储器访问请求。响应于存储器访问请求产生替代屏障。存储器访问请求可以是读请求。在存储器写入请求的情况下，在写入请求被处理之前生成替代屏障。替代障碍也可以响应于以与读取请求相同的地址的先前写入请求为条件的存储器读取请求而产生。一致性在分层存储器系统中实施，就好像从设备接收到不产生存储器屏障命令的存储器屏障命令一样。

98. 发明申请

US20110283083A1 Configuring Surrogate Memory Accessing Agents Using Non-Priviledged Processes 有权
标题翻译：使用非特权进程配置代理内存访问代理
公开(公告)号：US20110283083A1
公开(公告)日：2011-11-17
申请号：US12777324
申请日：2010-05-11
申请人： Thomas Andrew Sartorius
发明人： Thomas Andrew Sartorius
IPC分类号： G06F12/10
CPC分类号： G06F9/34 , G06F9/35 , G06F12/1027 , G06F12/1081 , Y02D10/13
摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.
摘要翻译：描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。数据值可以转换为第一个物理地址。虚拟地址可以转换为第二个物理地址。第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。

99. 发明申请

US20110202727A1 Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache 审中-公开
标题翻译：减少受害者缓存中重复行填充的装置和方法
公开(公告)号：US20110202727A1
公开(公告)日：2011-08-18
申请号：US12707968
申请日：2010-02-18
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache or the selected line is a write-through line. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译：技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中，或者所选行是直写行。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。防止所选线路的分配节省与分配相关联的功率。

100. 发明授权

US07984279B2 System and method for using a working global history register 有权
标题翻译：使用工作全球历史记录寄存器的系统和方法
公开(公告)号：US07984279B2
公开(公告)日：2011-07-19
申请号：US11556244
申请日：2006-11-03
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/00
CPC分类号： G06F9/3848 , G06F9/3804 , G06F9/3806 , G06F9/3861
摘要： A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register. The method further loads the branch history information into the second register during the second pipeline stage.
摘要翻译：公开了处理分支历史信息的方法。该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。该方法验证分支指令已被识别。该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中。该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

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