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1. 发明授权

US5809293A System and method for program execution tracing within an integrated processor 失效
标题翻译：集成处理器内程序执行跟踪的系统和方法
公开(公告)号：US5809293A
公开(公告)日：1998-09-15
申请号：US283128
申请日：1994-07-29
申请人： Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Joseph Irene , Harry I. Linzer , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Joseph Irene , Harry I. Linzer , Thomas Andrew Sartorius
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3648 , G06F2201/865
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。使用FIFO和串行逻辑电路来最小化从芯片广播信息所需的芯片引脚数。跟踪技术利用指令和数据断点调试功能来发出跟踪事件发生的外部跟踪工具。

2. 发明授权

US5724572A Method and apparatus for processing null terminated character strings 失效
标题翻译：处理空终止字符串的方法和装置
公开(公告)号：US5724572A
公开(公告)日：1998-03-03
申请号：US341789
申请日：1994-11-18
申请人： James N. Dieffenderfer , Harry I. Linzer , Thomas Andrew Sartorius
发明人： James N. Dieffenderfer , Harry I. Linzer , Thomas Andrew Sartorius
IPC分类号： G06F7/74 , G06F7/10
CPC分类号： G06F7/74 , Y10S707/99936
摘要： A method and apparatus for detecting the null byte at the end of a character string. The method and apparatus first logically concatenates two 32-bit input values into a single 64 bit value. Next, the 64-bit value is divided into 8 bytes. Then, a logical OR operation is performed on each byte and the results are put into an encoder. Finally, the encoder interprets the results of the OR operations and places output values into processor registers which indicate whether or where a null byte was detected.
摘要翻译：一种用于检测字符串末尾的空字节的方法和装置。该方法和设备首先将两个32位输入值逻辑级联为单个64位值。接下来，64位值被分为8个字节。然后，对每个字节执行逻辑或运算，并将结果放入编码器。最后，编码器解释OR操作的结果，并将输出值放在处理器寄存器中，指示是否检测到空字节。

3. 发明授权

US5926831A Methods and apparatus for control of speculative memory accesses 失效
标题翻译：用于控制存储器访问的方法和装置
公开(公告)号：US5926831A
公开(公告)日：1999-07-20
申请号：US731350
申请日：1996-10-11
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0215
摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.
摘要翻译：一种动态配置的存储器控制器，用于防止对非良好行为内存的推测性内存访问。可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

4. 发明授权

US06826747B1 System and method for tracing program instructions before and after a trace triggering event within a processor 失效
标题翻译：在处理器内跟踪触发事件之前和之后跟踪程序指令的系统和方法
公开(公告)号：US06826747B1
公开(公告)日：2004-11-30
申请号：US09412124
申请日：1999-10-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F1130
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event, and then providing the trace information externally from the processor.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令，然后从处理器向外部提供跟踪信息。

5. 发明授权

US5996092A System and method for tracing program execution within a processor before and after a triggering event 失效
标题翻译：在触发事件之前和之后跟踪处理器内的程序执行的系统和方法
公开(公告)号：US5996092A
公开(公告)日：1999-11-30
申请号：US760553
申请日：1996-12-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令。

6. 发明授权

US5910930A Dynamic control of power management circuitry 失效
标题翻译：电源管理电路的动态控制
公开(公告)号：US5910930A
公开(公告)日：1999-06-08
申请号：US868314
申请日：1997-06-03
申请人： James N. Dieffenderfer , George Filip Diniz , Thomas Andrew Sartorius
发明人： James N. Dieffenderfer , George Filip Diniz , Thomas Andrew Sartorius
IPC分类号： G06F1/32 , G04F5/00 , G06F1/00
CPC分类号： G06F1/3203
摘要： Method and apparatus for dynamic control of power management circuitry in a microprocessor. A clock and power management subsystem within the microprocessor contains clock generation and control logic and a powered-down mode register. The register is controlled by register control logic in the microprocessor and determines the powered-down mode of the various hardware units that make up the microprocessor. The clock generation and control logic also receives a powered-down mode enable signal from each of the hardware units. The hardware unit receive a re-power-up signal which, when activated and deactivated, can cause the hardware units to de-activate and activate, respectively, the powered-down mode enable signal. This combination of features allows continuous, repetitive, dynamic, hardware-controlled entry into exit from power saving modes without software intervention, thereby allowing the power saving modes to be used more often and more effectively for shorter periods of time than would be possible with software controlled power management.
摘要翻译：用于微处理器中功率管理电路的动态控制的方法和装置。微处理器内的时钟和电源管理子系统包含时钟生成和控制逻辑以及掉电模式寄存器。寄存器由微处理器中的寄存器控制逻辑控制，并确定构成微处理器的各种硬件单元的掉电模式。时钟生成和控制逻辑还从每个硬件单元接收掉电模式使能信号。硬件单元接收重新上电信号，当被激活和去激活时，可以使硬件单元分别去激活和激活掉电模式使能信号。这种功能的组合允许连续的，重复的，动态的，硬件控制的输入从省电模式退出而不需要软件干预，从而允许在比软件可能的更短的时间段内更频繁地使用节能模式受控电源管理。

7. 发明授权

US09092358B2 Memory management unit with pre-filling capability 有权
标题翻译：具有预充能力的内存管理单元
公开(公告)号：US09092358B2
公开(公告)日：2015-07-28
申请号：US13371506
申请日：2012-02-13
申请人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
发明人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
IPC分类号： G06F13/00 , G06F13/28 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译：用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数或基于访问模式动态地改变。预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

8. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

9. 发明授权

US08938602B2 Multiple sets of attribute fields within a single page table entry 有权
标题翻译：单个页表条目中的多组属性字段
公开(公告)号：US08938602B2
公开(公告)日：2015-01-20
申请号：US13565434
申请日：2012-08-02
申请人： Colin Christopher Sharp , Thomas Andrew Sartorius
发明人： Colin Christopher Sharp , Thomas Andrew Sartorius
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/656 , Y02D10/13
摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
摘要翻译：第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性，以及定义存储块的物理地址的物理地址位。

10. 发明授权

US08924685B2 Configuring surrogate memory accessing agents using non-priviledged processes 有权
标题翻译：使用非授权进程配置代理内存访问代理
公开(公告)号：US08924685B2
公开(公告)日：2014-12-30
申请号：US12777324
申请日：2010-05-11
申请人： Thomas Andrew Sartorius
发明人： Thomas Andrew Sartorius
IPC分类号： G06F12/10 , G06F9/34 , G06F9/35
CPC分类号： G06F9/34 , G06F9/35 , G06F12/1027 , G06F12/1081 , Y02D10/13
摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.
摘要翻译：描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。数据值可以转换为第一个物理地址。虚拟地址可以转换为第二个物理地址。第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。

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