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1. 发明申请

US20140006752A1 Qualifying Software Branch-Target Hints with Hardware-Based Predictions 审中-公开
标题翻译：合格软件分支 - 基于硬件预测的目标提示
公开(公告)号：US20140006752A1
公开(公告)日：2014-01-02
申请号：US13534649
申请日：2012-06-27
申请人： Michael William Morrow , James Norris Dieffenderfer , Thomas Andrew Sartorius , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
发明人： Michael William Morrow , James Norris Dieffenderfer , Thomas Andrew Sartorius , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
IPC分类号： G06F9/40
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.
摘要翻译：一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目的分支目标地址高速缓存，其中条目包括用于存储指令地址的标签字段，存储目标地址的目标字段，以及状态字段来存储状态值。在解码间接分支指令时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接分支指令的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目中的状态值，处理器将使用所存储的目标地址作为解码的间接分支指令的预测目标地址，或者将使用提供的软件提供的目标地址提示（如果可用）。

2. 发明申请

US20130311760A1 Multi Level Indirect Predictor using Confidence Counter and Program Counter Address Filter Scheme 有权
标题翻译：使用置信计数器和程序计数器地址过滤器的多级间接预测器
公开(公告)号：US20130311760A1
公开(公告)日：2013-11-21
申请号：US13472950
申请日：2012-05-16
申请人： Kulin N. Kothari , Michael William Morrow , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
发明人： Kulin N. Kothari , Michael William Morrow , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3848
摘要： The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.
摘要翻译：本公开涉及预测简单和多态分支指令。本公开的实施例检测到程序指令是分支指令，确定用于分支指令的程序计数器是否存储在程序计数器滤波器中，并且如果程序计数器存储在程序计数器滤波器中，则防止程序计数器从存储在第一级预测器中。

3. 发明授权

US09477478B2 Multi level indirect predictor using confidence counter and program counter address filter scheme 有权
标题翻译：多级间接预测器使用置信计数器和程序计数器地址过滤器方案
公开(公告)号：US09477478B2
公开(公告)日：2016-10-25
申请号：US13472950
申请日：2012-05-16
申请人： Kulin N. Kothari , Michael William Morrow , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
发明人： Kulin N. Kothari , Michael William Morrow , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel , Daren Eugene Streett
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3848
摘要： The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.
摘要翻译：本公开涉及预测简单和多态分支指令。本公开的实施例检测到程序指令是分支指令，确定用于分支指令的程序计数器是否存储在程序计数器滤波器中，并且如果程序计数器存储在程序计数器滤波器中，则防止程序计数器从存储在第一级预测器中。

4. 发明授权

US08341383B2 Method and a system for accelerating procedure return sequences 有权
标题翻译：方法和加速过程返回序列的系统
公开(公告)号：US08341383B2
公开(公告)日：2012-12-25
申请号：US11934264
申请日：2007-11-02
申请人： James Norris Dieffenderfer , Michael William Morrow
发明人： James Norris Dieffenderfer , Michael William Morrow
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/382
摘要： A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.
摘要翻译：公开了一种在从流水线处理器中的过程返回时从链接堆栈检索返回地址的方法。该方法识别可操作以从软件堆栈检索返回地址的检索指令。该方法进一步标识可分支到返回地址的分支指令。该方法响应于正在识别的指令和分支指令，并使用返回地址获取指令，从链接堆栈检索返回地址。

5. 发明申请

US20110320787A1 Indirect Branch Hint 审中-公开
标题翻译：间接分支提示
公开(公告)号：US20110320787A1
公开(公告)日：2011-12-29
申请号：US12824599
申请日：2010-06-28
申请人： James Norris Dieffenderfer , Michael William Morrow
发明人： James Norris Dieffenderfer , Michael William Morrow
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/30003 , G06F9/30101 , G06F9/322 , G06F9/3804 , G06F9/3842
摘要： A processor implements an apparatus and a method for predicting an indirect branch address. A target address generated by an instruction is automatically identified. A predicted next program address is prepared based on the target address before an indirect branch instruction utilizing the target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a predicted indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the predicted indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction.
摘要翻译：处理器实现用于预测间接分支地址的装置和方法。自动识别由指令生成的目标地址。在推测性地执行利用目标地址的间接分支指令之前，基于目标地址准备预测的下一个程序地址。该装置适当地采用寄存器来保存由程序指定的指令存储器地址作为间接分支指令的预测间接地址。该装置还采用下一个程序地址选择器，其从寄存器中选择预测的间接地址作为用于推测性地执行间接分支指令的下一个程序地址。

6. 发明授权

US08060701B2 Apparatus and methods for low-complexity instruction prefetch system 有权
标题翻译：低复杂度指令预取系统的装置和方法
公开(公告)号：US08060701B2
公开(公告)日：2011-11-15
申请号：US11608309
申请日：2006-12-08
申请人： Michael William Morrow , James Norris Dieffenderfer
发明人： Michael William Morrow , James Norris Dieffenderfer
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/3802 , G06F12/0862
摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
摘要翻译：当在指令高速缓存中发生错误时，使用预取技术来最小化错误率，存储器访问带宽和功率使用。当缺失发生时，预取技术之一运行。接收到在指令高速缓存中丢失的获取地址的通知。分析导致遗漏的提取地址，以确定提取地址的属性，并根据属性预取一行指令。该属性可以指示提取地址是非顺序操作的目标地址。另一个属性可以指示获取地址是非顺序操作的目标地址，并且目标地址大于高速缓存行中的X％。进一步的属性可以指示提取地址是指令高速缓存中的偶数地址。可以组合这些属性以确定是否预取。

7. 发明授权

US07917702B2 Data prefetch throttle 有权
标题翻译：数据预取油门
公开(公告)号：US07917702B2
公开(公告)日：2011-03-29
申请号：US11775320
申请日：2007-07-10
申请人： Michael William Morrow , James Norris Dieffenderfer
发明人： Michael William Morrow , James Norris Dieffenderfer
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.
摘要翻译：本文教导的系统和方法通过跟踪数据高速缓存的预取命中和整体命中来控制数据高速缓存的数据预取。基于预取命中的跟踪，数据高速缓存的数据预取被禁用，并且基于对整体命中的跟踪，为数据高速缓存启用数据预取。例如，在一个或多个实施例中，高速缓存控制器被配置为跟踪预取命中率，其反映涉及预取数据线的数据高速缓存上的命中百分比，并且如果预取命中率低于定义的阈值则禁用数据预取。高速缓存控制器还跟踪总体命中率，反映数据高速缓存命中的总体百分比（相对于未命中），如果总命中率低于定义的阈值，则可实现数据预取。

8. 发明申请

US20090119486A1 Method and a System for Accelerating Procedure Return Sequences 有权
标题翻译：加速程序返回序列的方法和系统
公开(公告)号：US20090119486A1
公开(公告)日：2009-05-07
申请号：US11934264
申请日：2007-11-02
申请人： James Norris Dieffenderfer , Michael William Morrow
发明人： James Norris Dieffenderfer , Michael William Morrow
IPC分类号： G06F9/312
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/382
摘要： A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.
摘要翻译：公开了一种在从流水线处理器中的过程返回时从链接堆栈检索返回地址的方法。该方法识别可操作以从软件堆栈检索返回地址的检索指令。该方法进一步标识可分支到返回地址的分支指令。该方法响应于正在识别的指令和分支指令，并使用返回地址获取指令，从链接堆栈检索返回地址。

9. 发明申请

US20090019229A1 Data Prefetch Throttle 有权
标题翻译：数据预取油门
公开(公告)号：US20090019229A1
公开(公告)日：2009-01-15
申请号：US11775320
申请日：2007-07-10
申请人： Michael William Morrow , James Norris Dieffenderfer
发明人： Michael William Morrow , James Norris Dieffenderfer
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.
摘要翻译：本文教导的系统和方法通过跟踪数据高速缓存的预取命中和整体命中来控制数据高速缓存的数据预取。基于预取命中的跟踪，数据高速缓存的数据预取被禁用，并且基于对整体命中的跟踪，为数据高速缓存启用数据预取。例如，在一个或多个实施例中，高速缓存控制器被配置为跟踪预取命中率，其反映涉及预取数据线的数据高速缓存上的命中百分比，并且如果预取命中率低于定义的阈值则禁用数据预取。高速缓存控制器还跟踪总体命中率，反映数据高速缓存命中的总体百分比（相对于未命中），如果总命中率低于定义的阈值，则可实现数据预取。

10. 发明申请

US20080140996A1 Apparatus and methods for low-complexity instruction prefetch system 有权
标题翻译：低复杂度指令预取系统的装置和方法
公开(公告)号：US20080140996A1
公开(公告)日：2008-06-12
申请号：US11608309
申请日：2006-12-08
申请人： Michael William Morrow , James Norris Dieffenderfer
发明人： Michael William Morrow , James Norris Dieffenderfer
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F12/0862
摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
摘要翻译：当在指令高速缓存中发生错误时，使用预取技术来最小化错误率，存储器访问带宽和功率使用。当缺失发生时，预取技术之一运行。接收到在指令高速缓存中丢失的获取地址的通知。分析导致遗漏的提取地址，以确定提取地址的属性，并根据属性预取一行指令。该属性可以指示提取地址是非顺序操作的目标地址。另一个属性可以指示获取地址是非顺序操作的目标地址，并且目标地址大于高速缓存行中的X％。进一步的属性可以指示提取地址是指令高速缓存中的偶数地址。可以组合这些属性以确定是否预取。

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