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    • 91. 发明申请
    • DC TO DC CONVERTER
    • 直流到直流转换器
    • US20110235367A1
    • 2011-09-29
    • US12878271
    • 2010-09-09
    • Takeshi UenoTetsuro Itakura
    • Takeshi UenoTetsuro Itakura
    • H02M3/24
    • H02M3/1563
    • A DC to DC converter includes an input terminal, an output terminal, first and second switches, an inductor, a smoothing unit, a first impedance element, a first resistor element, an operational amplifier and a control unit. The first switch is connected to the input terminal. The second switch is connected to the first switch and a ground terminal. The inductor is connected to the first switch and the output terminal. The smoothing unit is connected to the inductor and the ground terminal. The first impedance element is connected to the smoothing unit. The first resistor element is connected in series with the first impedance element. The operational amplifier is connected to the first impedance element. Reference voltage is added to the operational amplifier. The control unit controls the first and second switches according to a control signal outputted from the operational amplifier.
    • DC-DC转换器包括输入端子,输出端子,第一和第二开关,电感器,平滑单元,第一阻抗元件,第一电阻元件,运算放大器和控制单元。 第一个开关连接到输入端。 第二开关连接到第一开关和接地端子。 电感器连接到第一开关和输出端子。 平滑单元连接到电感器和接地端子。 第一阻抗元件连接到平滑单元。 第一电阻元件与第一阻抗元件串联连接。 运算放大器连接到第一阻抗元件。 参考电压加到运算放大器上。 控制单元根据从运算放大器输出的控制信号来控制第一和第二开关。
    • 92. 发明授权
    • Comparator and analog-to-digital converter using the same
    • 比较器和模数转换器使用相同
    • US07679428B2
    • 2010-03-16
    • US12175209
    • 2008-07-17
    • Mai NozawaDaisuke KuroseTakeshi UenoTetsuro Itakura
    • Mai NozawaDaisuke KuroseTakeshi UenoTetsuro Itakura
    • H03K5/22
    • H03K5/2481H03K5/249
    • A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal.
    • 比较器包括插入在电源端子和第一可变电阻器的一端之间的第一反相器,包括:第一FinFET,其具有用于接收正相输出信号的第一栅极端子和用于接收时钟的第二栅极端子 信号在第一电平和第二电平之间变化,使正相输出信号反相,并输出负相输出信号,并且插入在电源端和第二可变电阻的一端之间的第二反相器包括第二 FinFET具有用于接收负相输出信号的第三栅极端子,用于接收时钟信号的第四栅极端子和与第一FinFET相同的极性,反相负相输出信号,并输出正相输出信号。
    • 94. 发明申请
    • Magnetic field probe, current distribution measuring device and radio device
    • 磁场探头,电流分布测量装置和无线电装置
    • US20090322326A1
    • 2009-12-31
    • US12379250
    • 2009-02-17
    • Takayoshi ItoTetsuro ItakuraShuichi Obayashi
    • Takayoshi ItoTetsuro ItakuraShuichi Obayashi
    • G01R33/00
    • G01R33/0283G01R15/181
    • There is provided a magnetic field probe which includes: a probe body which is a coaxial cable wound to form a plurality of loop-like portions in planar view, the coaxial cable including an inner conductor, an insulator enclosing the inner conductor and an outer conductor enclosing the insulator; and a plurality of notches each of which is formed in each of the loop-like portions so that the outer conductor is divided to expose the inner conductor or the insulator, wherein: a plurality of outer conductor parts resulting from division by the notches are arranged to be electrically connected to each other, an one end of the inner conductor in the coaxial cable is connected to any one of the outer conductor parts; and winding directions of at least one of a pair of loop-like portions among the loop-like portions are reversed from each other in planar view.
    • 提供了一种磁场探针,其包括:探针体,其是在平面图中缠绕以形成多个环状部分的同轴电缆,所述同轴电缆包括内部导体,包围内部导体的绝缘体和外部导体 封闭绝缘体; 以及多个凹口,每个凹槽形成在每个环状部分中,使得外部导体被分割以暴露内部导体或绝缘体,其中:由凹口划分产生的多个外部导体部件布置 彼此电连接,同轴电缆中的内部导体的一端连接到任何一个外部导体部分; 并且在环状部分中的一对环状部分中的至少一个的卷绕方向在平面视图中彼此相反。
    • 97. 发明授权
    • Transconductor
    • 跨导体
    • US07538585B2
    • 2009-05-26
    • US11847503
    • 2007-08-30
    • Rui ItoTetsuro Itakura
    • Rui ItoTetsuro Itakura
    • H02M11/00H03F3/45
    • H03G1/0029H03F1/3211H03F3/45179H03F3/45475H03F2203/45318H03F2203/45342H03F2203/45352H03F2203/45398H03H11/04
    • Disclosed is a transconductor including: first and second transistors each having first and second gates, the first and second gates being independently controlled, differential voltage input being supplied between the one first gate and the other first gate, the one source and the other source being connected, a first control voltage being commonly given to both of the second gates, and the drains being differential current output terminals; third and fourth transistors each having the same connection as the first and second transistors, each of the one drain and the other drain being connected with either of the one drain and the other drain of the first and the second transistors so that polarities are opposite to each other; and a current source connected with both of the sources of the first and the second transistors and both of the sources of the third and the fourth transistors.
    • 公开了一种跨导体,包括:第一和第二晶体管,每个具有第一和第二栅极,第一和第二栅极被独立地控制,差分电压输入被提供在一个第一栅极和另一个第一栅极之间,一个源极和另一个源极 所述第一控制电压通常被提供给所述第二栅极,并且所述漏极是差动电流输出端子; 第三和第四晶体管各自具有与第一和第二晶体管相同的连接,一个漏极和另一个漏极中的每一个与第一和第二晶体管的一个漏极和另一个漏极中的任一个连接,使得极性与 彼此; 以及与第一和第二晶体管的源极以及第三和第四晶体管的源极两者连接的电流源。
    • 98. 发明授权
    • Differential amplifying circuit
    • 差分放大电路
    • US07532069B2
    • 2009-05-12
    • US12173431
    • 2008-07-15
    • Tomohiko ItoTetsuro Itakura
    • Tomohiko ItoTetsuro Itakura
    • H03F3/45
    • H03F3/45179
    • Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
    • 公开了一种包括放大电路的差分放大电路,其中1)第六晶体管的漏极连接到第八晶体管的漏极,第十晶体管的漏极连接到第四晶体管的漏极,以及2) 第四(或第八)和第十(或第六)晶体管(每单位栅极长度转换,并且随后的栅极宽度相同)的栅极宽度的总和与第五(或第九)晶体管 几乎与第一(或第三)和第二(或第四)电流源电路之间的电流比成比例,第四(或第八)晶体管的栅极宽度等于或大于第十(或第六)晶体管的栅极宽度 。