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1. 发明申请

US20080284634A1 DIFFERENTIAL AMPLIFYING CIRCUIT 失效
标题翻译：差分放大电路
公开(公告)号：US20080284634A1
公开(公告)日：2008-11-20
申请号：US12173431
申请日：2008-07-15
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/60
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译：公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2）第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度。

2. 发明申请

US20090184857A1 A/D CONVERTING APPARATUS 失效
标题翻译： A / D转换装置
公开(公告)号：US20090184857A1
公开(公告)日：2009-07-23
申请号：US12349180
申请日：2009-01-06
申请人： Masanori Furuta , Tomohiko Ito , Takafumi Yamaji , Tetsuro Itakura
发明人： Masanori Furuta , Tomohiko Ito , Takafumi Yamaji , Tetsuro Itakura
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/162 , H03M1/164 , H03M1/468
摘要： An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.
摘要翻译： A / D转换装置包括：第一A / D转换器，对具有D / A转换器的模拟输入信号进行采样以产生用于与模拟输入信号连续比较的比较信号，信号发生器在模拟输入端之间产生差分信号信号和比较信号，以及比较器，用于将比较信号与标准值进行比较，以产生呈现高位的第一数字信号; 放大器，用于放大差分信号以产生残留信号; 以及第二A / D转换器，用于对残留信号进行采样以产生呈现低阶位的第二数字信号。

3. 发明申请

US20070210869A1 DIFFERENTIAL AMPLIFYING CIRCUIT 有权
标题翻译：差分放大电路
公开(公告)号：US20070210869A1
公开(公告)日：2007-09-13
申请号：US11618071
申请日：2006-12-29
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译：公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2）第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度。

4. 发明授权

US07532069B2 Differential amplifying circuit 失效
标题翻译：差分放大电路
公开(公告)号：US07532069B2
公开(公告)日：2009-05-12
申请号：US12173431
申请日：2008-07-15
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译：公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2）第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管几乎与第一（或第三）和第二（或第四）电流源电路之间的电流比成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度。

5. 发明授权

US07414472B2 Differential amplifying circuit 有权
标题翻译：差分放大电路
公开(公告)号：US07414472B2
公开(公告)日：2008-08-19
申请号：US11618071
申请日：2006-12-29
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译：公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2）第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度。

6. 发明授权

US08390498B2 Comparing circuit and parallel analog-to-digital converter 失效
标题翻译：比较电路和并行模数转换器
公开(公告)号：US08390498B2
公开(公告)日：2013-03-05
申请号：US13207121
申请日：2011-08-10
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/12
CPC分类号： H03M1/1023 , H03K5/2481 , H03M1/365
摘要： First and second resistor series divide a predetermined voltage range to generate first reference voltages and second reference voltages, respectively. First and second switch controlling circuits select respective ones of the first reference voltages and the second reference voltages. A comparing unit generates a logical signal representing a logical value by comparing a combined transistor current based on the selected first and second reference voltages with a transistor current based on an input signal. The first switch controlling circuit specifies two adjacent first reference voltages where the logical value is inverted by sequentially selecting the first reference voltages, and determines to select one of the adjacent reference voltages. Te second switch controlling circuit specifies two adjacent second reference voltages where the logical value is inverted by sequentially selecting the second reference voltages, and determines to select one of the adjacent reference voltages.
摘要翻译：第一和第二电阻器串分割预定电压范围以分别产生第一参考电压和第二参考电压。第一和第二开关控制电路选择第一参考电压和第二参考电压中的相应的一个。比较单元通过基于所选择的第一和第二参考电压与基于输入信号的晶体管电流比较组合的晶体管电流来产生表示逻辑值的逻辑信号。第一开关控制电路通过顺序选择第一参考电压来指定逻辑值反相的两个相邻的第一参考电压，并且确定选择相邻参考电压之一。 Te第二开关控制电路指定两个相邻的第二参考电压，其中逻辑值通过顺序选择第二参考电压而被反相，并且确定选择相邻参考电压之一。

7. 发明授权

US07940200B2 Calibration method, A/D converter, and radio device 有权
标题翻译：校准方法，A / D转换器和无线电设备
公开(公告)号：US07940200B2
公开(公告)日：2011-05-10
申请号：US12637211
申请日：2009-12-14
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/10
CPC分类号： H03M1/1023 , H03M1/0682 , H03M1/205 , H03M1/365 , H03M1/745
摘要： There is disclosed a calibration method for an A/D converter. The A/D converter includes a first amplifier to amplify first and second voltage signals, a second amplifier to amplify the first and second voltage signals amplified by the first amplifier, and a comparator to compare the first and second voltage signals amplified by the second amplifier. The calibration method performs short-circuiting input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a first result, calibrating output voltage of the second amplifier according to the first result, short-circuiting input ports of the first amplifier, opening the short-circuited input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a second result, and calibrating output voltage of the first amplifier according to the second result.
摘要翻译：公开了一种用于A / D转换器的校准方法。 A / D转换器包括：放大第一和第二电压信号的第一放大器;放大由第一放大器放大的第一和第二电压信号的第二放大器;以及比较器，用于比较由第二放大器放大的第一和第二电压信号; 。校准方法执行第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第一结果，根据第一结果校准第二放大器的输出电压，短路输入端口第一放大器，打开第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第二结果，并根据第二结果校准第一放大器的输出电压。

8. 发明授权

US07884749B2 A/D converting apparatus 失效
标题翻译： A / D转换装置
公开(公告)号：US07884749B2
公开(公告)日：2011-02-08
申请号：US12349180
申请日：2009-01-06
申请人： Masanori Furuta , Tomohiko Ito , Takafumi Yamaji , Tetsuro Itakura
发明人： Masanori Furuta , Tomohiko Ito , Takafumi Yamaji , Tetsuro Itakura
IPC分类号： H03M1/38
CPC分类号： H03M1/1215 , H03M1/162 , H03M1/164 , H03M1/468
摘要： An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.
摘要翻译： A / D转换装置包括：第一A / D转换器，对具有D / A转换器的模拟输入信号进行采样以产生用于与模拟输入信号连续比较的比较信号，信号发生器在模拟输入端之间产生差分信号信号和比较信号，以及比较器，用于将比较信号与标准值进行比较，以产生呈现高位的第一数字信号; 放大器，用于放大差分信号以产生残余信号; 以及第二A / D转换器，用于对残留信号进行采样以产生呈现低阶位的第二数字信号。

9. 发明申请

US20100142653A1 A/D CONVERSION APPARATUS, A/D CONVERSION METHOD, AND COMMUNICATION APPARATUS 有权
标题翻译： A / D转换装置，A / D转换方法和通信装置
公开(公告)号：US20100142653A1
公开(公告)日：2010-06-10
申请号：US12553315
申请日：2009-09-03
申请人： Masanori Furuta , Tomohiko Ito , Tetsuro Itakura
发明人： Masanori Furuta , Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/34 , H04L27/06
CPC分类号： H04L27/06 , H03M1/0682 , H03M1/468 , H03M1/804
摘要： An A/D conversion apparatus includes: a first and a second D/A converter to sample an analog signal and successively compare the analog signal and a reference signal to generate a first and a second comparison signal respectively; a first comparator to compare the first comparison signal generated by the first D/A converter with a benchmark signal; a second comparator to compare the second comparison signal generated by the second D/A converter with the benchmark signal; and a converter to convert the analog signal to a digital signal according to results of the comparisons by the first and second comparators.
摘要翻译： A / D转换装置包括：第一和第二D / A转换器，对模拟信号进行采样，并连续地比较模拟信号和参考信号，分别产生第一和第二比较信号; 第一比较器，用于将由第一D / A转换器产生的第一比较信号与基准信号进行比较; 第二比较器，用于将由第二D / A转换器产生的第二比较信号与基准信号进行比较; 以及根据第一和第二比较器的比较结果将模拟信号转换为数字信号的转换器。

10. 发明申请

US20120235844A1 Comparing Circuit and Parallel Analog-To-Digital Converter 失效
标题翻译：比较电路和并行模数转换器
公开(公告)号：US20120235844A1
公开(公告)日：2012-09-20
申请号：US13207121
申请日：2011-08-10
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/12 , H03K5/153
CPC分类号： H03M1/1023 , H03K5/2481 , H03M1/365
摘要： First and second resistor series divide a predetermined voltage range to generate first reference voltages and second reference voltages, respectively. First and second switch controlling circuits select respective ones of the first reference voltages and the second reference voltages. A comparing unit generates a logical signal representing a logical value by comparing a combined transistor current based on the selected first and second reference voltages with a transistor current based on an input signal. The first switch controlling circuit specifies two adjacent first reference voltages where the logical value is inverted by sequentially selecting the first reference voltages, and determines to select one of the adjacent reference voltages. Te second switch controlling circuit specifies two adjacent second reference voltages where the logical value is inverted by sequentially selecting the second reference voltages, and determines to select one of the adjacent reference voltages.
摘要翻译：第一和第二电阻器串分割预定电压范围以分别产生第一参考电压和第二参考电压。第一和第二开关控制电路选择第一参考电压和第二参考电压中的相应的一个。比较单元通过基于所选择的第一和第二参考电压与基于输入信号的晶体管电流比较组合的晶体管电流来产生表示逻辑值的逻辑信号。第一开关控制电路通过顺序选择第一参考电压来指定逻辑值反相的两个相邻的第一参考电压，并且确定选择相邻参考电压之一。 Te第二开关控制电路指定两个相邻的第二参考电压，其中逻辑值通过顺序选择第二参考电压而被反相，并且确定选择相邻参考电压之一。

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