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1. 发明授权

US07865163B2 Time constant automatic adjusting circuit, filter circuit system, and method of automatically adjusting time constant 失效
标题翻译：时间常数自动调节电路，滤波电路系统及自动调整时间常数的方法
公开(公告)号：US07865163B2
公开(公告)日：2011-01-04
申请号：US12407442
申请日：2009-03-19
申请人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
发明人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
IPC分类号： H04B1/10
CPC分类号： H03H11/1291
摘要： A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.
摘要翻译：时间常数自动调整电路包括：滤波器电路，改变输入时钟信号的相位以输出时钟信号; 相位比较电路，将滤波器电路的输出信号的相位与时钟信号的相位进行比较，并且当输出信号的相位和时钟信号的相位相同时输出预定电压; 至少三个比较器将输出电压与多个不同电压进行比较; 根据比较器的输出结果，计数至少三个不同电压中的任何一个的输出位的数量的递减计数器; 以及控制电路根据由升降计数器计数的输出位数来改变滤波电路的时间常数。

2. 发明申请

US20090179696A1 TIME CONSTANT AUTOMATIC ADJUSTING CIRCUIT, FILTER CIRCUIT SYSTEM, AND METHOD OF AUTOMATICALLY ADJUSTING TIME CONSTANT 失效
标题翻译：时间不变的自动调节电路，滤波电路系统和自动调整时间的方法
公开(公告)号：US20090179696A1
公开(公告)日：2009-07-16
申请号：US12407442
申请日：2009-03-19
申请人： Osamu WATANABE , Rui ITO , Shigehito SAIGUSA , Tetsuro ITAKURA
发明人： Osamu WATANABE , Rui ITO , Shigehito SAIGUSA , Tetsuro ITAKURA
IPC分类号： H03K5/00
CPC分类号： H03H11/1291
摘要： A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.
摘要翻译：时间常数自动调整电路包括：滤波器电路，改变输入时钟信号的相位以输出时钟信号; 相位比较电路，将滤波器电路的输出信号的相位与时钟信号的相位进行比较，并且当输出信号的相位和时钟信号的相位相同时输出预定电压; 至少三个比较器将输出电压与多个不同电压进行比较; 根据比较器的输出结果，计数至少三个不同电压中的任何一个的输出位的数量的递减计数器; 以及控制电路根据由升降计数器计数的输出位数来改变滤波电路的时间常数。

3. 发明授权

US07123082B2 Variable time constant circuit and filter circuit using the same 失效
标题翻译：可变时间常数电路和滤波电路使用相同
公开(公告)号：US07123082B2
公开(公告)日：2006-10-17
申请号：US11258934
申请日：2005-10-27
申请人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
发明人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
IPC分类号： H04B1/10
CPC分类号： H03H11/32 , H03F3/345 , H03F3/45475 , H03F2203/45511 , H03F2203/45512 , H03F2203/45592 , H03F2203/45652 , H03H11/1291 , H03H11/245
摘要： A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.
摘要翻译：可变时间常数电路包括反相放大器，其具有放大器输入端和连接到信号输出端的放大器输出端，并且反相输入到放大器输入端的信号，第一和第二电阻串联在第信号输入端子和放大器输入端子，连接在放大器输入端子和放大器输出端子之间的电容器，场效应晶体管，其包括连接到第一和第二电阻器的接合点的栅极端子，源极端子保持恒定电位和连接到放大器输入端子的漏极端子，晶体管根据栅极端子和源极端子之间的电压流过漏极端子，以及控制电路，其控制晶体管的电压 - 电流转换比根据时间常数控制信号。

4. 发明申请

US20060033560A1 Variable time constant circuit and filter circuit using the same 失效
公开(公告)号：US20060033560A1
公开(公告)日：2006-02-16
申请号：US11258934
申请日：2005-10-27
申请人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
发明人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
IPC分类号： H03K5/00
CPC分类号： H03H11/32 , H03F3/345 , H03F3/45475 , H03F2203/45511 , H03F2203/45512 , H03F2203/45592 , H03F2203/45652 , H03H11/1291 , H03H11/245
摘要： A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.

5. 发明授权

US07733186B2 Bias circuit and amplifier using the same 失效
标题翻译：偏置电路和放大器使用相同
公开(公告)号：US07733186B2
公开(公告)日：2010-06-08
申请号：US12404520
申请日：2009-03-16
申请人： Masahiro Hosoya , Rui Ito
发明人： Masahiro Hosoya , Rui Ito
IPC分类号： H03F3/04
CPC分类号： G05F3/26 , G05F3/20 , H03F1/301 , H03F3/45475 , H03F2200/447 , H03F2203/45244
摘要： A bias circuit including: a first current source which generates a first current; a second current source which generates a second current having a temperature-to-output current characteristic that an output current characteristic increases or decreases with a change in temperature to intersect with that of the first current; a first current-voltage conversion circuit which converts the first current to a first voltage; a second current-voltage conversion circuit which has an input terminal and converts a current inputted into the input terminal to a second voltage; a comparison circuit which compares the first voltage and the second voltage and generates a third current according to a result of the comparison; an addition unit which adds the third current to the second current and inputs a resulting current to the input terminal; and a voltage-current conversion circuit which converts the second voltage to a fourth current for bias.
摘要翻译：一种偏置电路，包括：产生第一电流的第一电流源; 产生第二电流的第二电流，所述第二电流具有输出电流特性随温度变化而与第一电流相交的温度 - 输出电流特性的增加或减小; 第一电流电压转换电路，其将第一电流转换为第一电压; 第二电流电压转换电路，其具有输入端子，并将输入到所述输入端子的电流转换为第二电压; 比较电路，其比较所述第一电压和所述第二电压，并根据所述比较结果产生第三电流; 加法单元，其将所述第三电流加到所述第二电流，并将所得电流输入到所述输入端; 以及电压 - 电流转换电路，其将第二电压转换为用于偏置的第四电流。

6. 发明授权

US07538585B2 Transconductor 失效
标题翻译：跨导体
公开(公告)号：US07538585B2
公开(公告)日：2009-05-26
申请号：US11847503
申请日：2007-08-30
申请人： Rui Ito , Tetsuro Itakura
发明人： Rui Ito , Tetsuro Itakura
IPC分类号： H02M11/00 , H03F3/45
CPC分类号： H03G1/0029 , H03F1/3211 , H03F3/45179 , H03F3/45475 , H03F2203/45318 , H03F2203/45342 , H03F2203/45352 , H03F2203/45398 , H03H11/04
摘要： Disclosed is a transconductor including: first and second transistors each having first and second gates, the first and second gates being independently controlled, differential voltage input being supplied between the one first gate and the other first gate, the one source and the other source being connected, a first control voltage being commonly given to both of the second gates, and the drains being differential current output terminals; third and fourth transistors each having the same connection as the first and second transistors, each of the one drain and the other drain being connected with either of the one drain and the other drain of the first and the second transistors so that polarities are opposite to each other; and a current source connected with both of the sources of the first and the second transistors and both of the sources of the third and the fourth transistors.
摘要翻译：公开了一种跨导体，包括：第一和第二晶体管，每个具有第一和第二栅极，第一和第二栅极被独立地控制，差分电压输入被提供在一个第一栅极和另一个第一栅极之间，一个源极和另一个源极所述第一控制电压通常被提供给所述第二栅极，并且所述漏极是差动电流输出端子; 第三和第四晶体管各自具有与第一和第二晶体管相同的连接，一个漏极和另一个漏极中的每一个与第一和第二晶体管的一个漏极和另一个漏极中的任一个连接，使得极性与彼此; 以及与第一和第二晶体管的源极以及第三和第四晶体管的源极两者连接的电流源。

7. 发明申请

US20080309436A1 MULTI-INPUT MULTI-OUTPUT AMPLIFIER, AN ACTIVE INDUCTOR, A FILTER AND A RADIO COMMUNICATION DEVICE 审中-公开
标题翻译：多输入多输出放大器，有源电感器，滤波器和无线电通信装置
公开(公告)号：US20080309436A1
公开(公告)日：2008-12-18
申请号：US12051098
申请日：2008-03-19
申请人： Takafumi Yamaji , Rui Ito , Tetsuro Itakura
发明人： Takafumi Yamaji , Rui Ito , Tetsuro Itakura
IPC分类号： H03H11/00 , H03F3/00 , H04L25/00
CPC分类号： H04L27/3854 , H03F3/19 , H03F3/211 , H03F2200/451 , H04B1/40 , H04L27/233
摘要： A non-inverting amplifier includes n external input terminals which receive n (n≧3) input voltage signals having a constant sum of voltages, respectively, n amplification units each including n−1 internal input terminals connected to n−1 terminals of the n external input terminals in a different combination for each of the amplification units, n−1 voltage-to-current converters which convert input voltage signals from the internal input terminals into current signals, and a load which converts an added current signal obtained by adding up the current signals into an output voltage signal, and n external output terminals which output n output voltage signals from the n amplification units.
摘要翻译：非反相放大器包括n个外部输入端子，其分别接收具有恒定电压和的n（n> = 3）个输入电压信号，n个放大单元，每个放大单元包括n-1个内部输入端子，其连接到 n个不同组合的外部输入端子用于每个放大单元，n-1个电压 - 电流转换器，其将来自内部输入端子的输入电压信号转换为电流信号;以及负载，其将通过添加获得的相加电流信号将电流信号提升为输出电压信号，以及从n个放大单元输出n个输出电压信号的n个外部输出端子。

8. 发明授权

US07778358B2 Receiver, wireless device and method for cancelling a DC offset component 失效
标题翻译：接收机，无线设备和消除DC偏移分量的方法
公开(公告)号：US07778358B2
公开(公告)日：2010-08-17
申请号：US11851851
申请日：2007-09-07
申请人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
发明人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： H04L25/06
摘要： A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.
摘要翻译：接收机包括用于存储由模拟电路产生的DC偏移量的存储器; 放大器 DC偏移量发生器，用于产生从放大器放大的接收信号中去除的第一偏移值和第二偏移值; 第一DC偏移分量去除单元，用于从放大器之前的接收信号中去除第一DC偏移值; 第二DC偏移分量去除单元，用于从放大器之后的接收信号中去除第二DC偏移值; 以及更新单元，用于根据由DC偏移量产生器生成的第二DC偏移值来更新存储在存储器中的DC偏移量。将第二DC偏移值的最大值设定为大于放大器的增益乘以第一DC偏移值的最小分辨率值。

9. 发明授权

US07583948B2 Time constant automatic adjusting circuit, filter circuit system, and method of automatically adjusting time constant 失效
标题翻译：时间常数自动调节电路，滤波电路系统及自动调整时间常数的方法
公开(公告)号：US07583948B2
公开(公告)日：2009-09-01
申请号：US11411939
申请日：2006-04-27
申请人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
发明人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
IPC分类号： H04B1/00
CPC分类号： H03H11/1291
摘要： A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.
摘要翻译：时间常数自动调整电路包括：滤波器电路，改变输入时钟信号的相位以输出时钟信号; 相位比较电路，将滤波器电路的输出信号的相位与时钟信号的相位进行比较，并且当输出信号的相位和时钟信号的相位相同时输出预定电压; 至少三个比较器将输出电压与多个不同电压进行比较; 根据比较器的输出结果，计数至少三个不同电压中的任何一个的输出位的数量的递减计数器; 以及控制电路根据由升降计数器计数的输出位数来改变滤波电路的时间常数。

10. 发明申请

US20080274714A1 AMPLIFIER, FILTER USING THE SAME, AND RADIO COMMUNICATION DEVICE 审中-公开
公开(公告)号：US20080274714A1
公开(公告)日：2008-11-06
申请号：US12170989
申请日：2008-07-10
申请人： Takafumi Yamaji , Rui Ito , Tetsuro Itakura
发明人： Takafumi Yamaji , Rui Ito , Tetsuro Itakura
IPC分类号： H04B1/16 , H03F3/45 , H03B1/00
CPC分类号： H03F3/193 , H03F3/45085 , H03F3/45183 , H03F2203/45352
摘要： An amplifier includes an amplification unit which amplify a first difference between first and second input signals, a second difference between second and third input signals and a third difference between third and first input signals by a differential mode gain, and amplify an average of the first, second and third input signal by a common mode gain, for outputting a first output signal corresponding to a sum of the amplified first difference and the amplified average, a second output signal corresponding to a sum of the amplified second difference and the amplified average, and a third output signal corresponding to a sum of the amplified third difference and amplified average; first, second; and a reduction circuit which reduces the common mode gain less than the differential mode gain.

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