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91. 发明授权

US06984975B2 Magnetic displacement sensor for sensing the position of an object 失效
标题翻译：用于感测物体位置的磁位移传感器
公开(公告)号：US06984975B2
公开(公告)日：2006-01-10
申请号：US10683734
申请日：2003-10-10
申请人： Fusayoshi Aruga , Junichi Nakajyo , Shogo Momose , Hiroshi Nakamura
发明人： Fusayoshi Aruga , Junichi Nakajyo , Shogo Momose , Hiroshi Nakamura
IPC分类号： G01B7/14
CPC分类号： G01D5/204
摘要： A displacement sensor for sensing the relative position of an object to be detcted is provided. The displacement sensor includes a core body having a core center portion and core end portions that are continuously formed on both sides of the core center portion. Magnetizing coils and detecting coils are wound around the core body such that they are lined on an axis of the core body. One of the magnetizing coils and detecting coils is placed at the core center portion while the other ones of the magnetizing coils and detctin coils are placed at the core end portions in the axial direction. The width of the core end portions in the direction perpendicular to the axial direction of the core body is substantially the same and is smaller than the width of the core center portion.
摘要翻译：提供了用于感测被检测物体的相对位置的位移传感器。位移传感器包括具有芯部中心部分的芯体和连续地形成在芯部中心部分两侧的芯部端部。磁化线圈和检测线圈缠绕在芯体上，使得它们被排列在芯体的轴线上。磁化线圈和检测线圈中的一个放置在芯中心部分，而另一个磁化线圈和定子线圈被放置在轴向的芯部端部。芯端部在与芯体的轴向垂直的方向上的宽度大致相同且小于芯心部的宽度。

92. 发明授权

US06980423B2 Tablet interlocking mechanism 失效
标题翻译：片联锁机构
公开(公告)号：US06980423B2
公开(公告)日：2005-12-27
申请号：US10717329
申请日：2003-11-18
申请人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin P. Riddiford
发明人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin P. Riddiford
IPC分类号： G06F1/16
CPC分类号： G06F1/162 , G06F1/1679 , G06F1/1688 , G06F2200/1614 , Y10S248/917 , Y10T292/0849 , Y10T292/11
摘要： An apparatus has a body having a channel. A display support member has a first end pivotally coupled to the body and a second end. A display housing has a bottom portion. The display housing is pivotally coupled to the second end of the display support member. A first latch member is coupled to the bottom portion of the display housing. The first latch member is adapted to be received by the channel and hold the display housing.
摘要翻译：装置具有具有通道的主体。显示器支撑构件具有枢转地联接到主体的第一端和第二端。显示器壳体具有底部。显示器壳体枢转地联接到显示器支撑构件的第二端。第一闩锁构件联接到显示器壳体的底部。第一闩锁构件适于被通道接收并且保持显示器壳体。

93. 发明授权

US06967892B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06967892B2
公开(公告)日：2005-11-22
申请号：US10804094
申请日：2004-03-19
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C16/04
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

94. 发明申请

US20050237829A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050237829A1
公开(公告)日：2005-10-27
申请号：US11104599
申请日：2005-04-13
申请人： Hiroshi Nakamura , Tomoharu Tanaka
发明人： Hiroshi Nakamura , Tomoharu Tanaka
IPC分类号： G11C16/06 , G11C7/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/30
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/30
摘要： A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.
摘要翻译：非易失性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元单元格阵列。在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二写入中间电压。

95. 发明申请

US20050190632A1 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line 有权
标题翻译：半导体存储器件仅使用单通道晶体管对所选字线施加电压
公开(公告)号：US20050190632A1
公开(公告)日：2005-09-01
申请号：US11115364
申请日：2005-04-27
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C11/413 , G11C16/04 , G11C16/06 , G11C16/08 , H01L27/115 , G11C8/00
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/3459 , H01L27/115
摘要： A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
摘要翻译：本文公开的半导体存储器件包括存储单元阵列，其中存储单元以矩阵形式布置，行解码器电路用于选择该存储单元阵列中的字线并向所选字线施加电压。解码器电路包括多个第一导电类型的第一晶体管，其中每个电流路径的一端直接连接到每个字线，以及与第一导电类型相反的第二导电类型的第二晶体管，用于施加在对所选择的字线施加电压的操作时，连接到所选字线的第一晶体管的栅极的电压。对所选择的字线施加电压仅由第一导电类型的第一晶体管执行。

96. 发明申请

US20050190602A1 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US20050190602A1
公开(公告)日：2005-09-01
申请号：US11119744
申请日：2005-05-03
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/02 , G11C7/06 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

97. 发明授权

US06924690B2 Voltage switching circuit 有权
标题翻译：电压开关电路
公开(公告)号：US06924690B2
公开(公告)日：2005-08-02
申请号：US10292527
申请日：2002-11-13
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： H01L21/822 , G11C5/14 , G11C8/08 , G11C16/08 , G11C16/12 , G11C16/30 , H01L27/04 , H01L27/088 , H01L27/092 , H03K17/0814 , H03K17/10 , H03K17/693 , H03K19/003 , H03K19/0185 , H03L7/06 , H03K17/00
CPC分类号： G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H01L27/088 , H01L27/092 , H03K17/08142 , H03K17/102 , H03K17/693 , H03K19/00315 , H03K19/018521
摘要： A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.
摘要翻译：公开了一种电压切换电路，其由最小数量的晶体管构成，并且通过由单个耗尽型晶体管执行的高电压截止和电源电压传递函数在两个串联连接之间共享来防止阈值电压裕度降低耗尽型晶体管的栅极绝缘膜厚度或阈值电压不同。因此，在不使用涉及图案面积增加的增强型晶体管的情况下，可以提供电压切换电路，其芯片面积小，成本低，成品率和可靠性高，并且提供具有低电源电压的稳定操作，这是不可能的一个耗尽晶体管。

98. 发明申请

US20050094478A1 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050094478A1
公开(公告)日：2005-05-05
申请号：US10989372
申请日：2004-11-17
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C7/20 , G11C16/20 , G11C29/00 , G11C8/02
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

99. 发明申请

US20050094441A1 Semiconductor memory device in which source line potential is controlled in accordance with data programming mode 有权
标题翻译：根据数据编程模式控制源极线电位的半导体存储器件
公开(公告)号：US20050094441A1
公开(公告)日：2005-05-05
申请号：US11005594
申请日：2004-12-06
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C2216/16
摘要： There is provided a semiconductor memory device, which realizes rewriting of data in the memory cell by applying a potential difference between the gate and the source, or applying a potential difference between the gate and the drain, which is larger than the power supply voltage. This semiconductor memory device is provided with a source line potential control circuit configured to control the source line potential. The source line potential control circuit sets the source line potential at the time of the mode for programming “1” data in a plurality of blocks in one package to a level lower than at the normal-data programming mode.
摘要翻译：提供了一种半导体存储器件，其通过施加栅极和源极之间的电位差或施加大于电源电压的栅极和漏极之间的电位差来实现对存储器单元中的数据的重写。该半导体存储器件设置有用于控制源极线电位的源极线电位控制电路。源极线电位控制电路将用于将一个封装中的多个块中的“1”数据编程的模式的源极线电位设置为低于正常数据编程模式的电平。

100. 发明授权

US06882569B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06882569B2
公开(公告)日：2005-04-19
申请号：US10918686
申请日：2004-08-13
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.
摘要翻译：一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

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