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91. 发明授权

US08642407B2 Devices having reduced susceptibility to soft-error effects and method for fabrication 有权
标题翻译：降低了对软错误效应的敏感性的装置和制造方法
公开(公告)号：US08642407B2
公开(公告)日：2014-02-04
申请号：US12939506
申请日：2010-11-04
申请人： Tak H. Ning , Philip J. Oldiges
发明人： Tak H. Ning , Philip J. Oldiges
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878
摘要： A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.
摘要翻译：绝缘体上半导体（SOI）衬底互补金属氧化物半导体（CMOS）器件和制造方法包括p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 PFET和NFET中的每一个包括第一类材料和源极和漏极区的晶体管体。源极和漏极区域具有第二类型的材料，使得源极和漏极区域中的注入电荷大于晶体管本体中的寄生电荷以降低寄生双极性电流增益，增加临界电荷（Qcrit）并降低对软件的灵敏度错误。

92. 发明授权

US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

93. 发明申请

US20120289018A1 SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译： SOI SiGe-BASE横向双极晶体管晶体管
公开(公告)号：US20120289018A1
公开(公告)日：2012-11-15
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

94. 发明申请

US20120190192A1 Metal-Semiconductor Intermixed Regions 有权
公开(公告)号：US20120190192A1
公开(公告)日：2012-07-26
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

95. 发明授权

US08063424B2 Embedded photodetector apparatus in a 3D CMOS chip stack 有权
标题翻译： 3D CMOS芯片堆叠中的嵌入式光电探测器
公开(公告)号：US08063424B2
公开(公告)日：2011-11-22
申请号：US12618895
申请日：2009-11-16
申请人： Fadi H. Gebara , Tak H. Ning , Qiqing C. Ouyang , Jeremy D. Schaub
发明人： Fadi H. Gebara , Tak H. Ning , Qiqing C. Ouyang , Jeremy D. Schaub
IPC分类号： H01L31/062
CPC分类号： H01L27/14634 , H01L21/743 , H01L23/481 , H01L27/1203 , H01L27/14636 , H01L27/14647 , H01L27/1469 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181
摘要： An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.
摘要翻译：提供了一种用于具有CMOS芯片和一个或多个薄化CMOS层的三维互补金属氧化物半导体（CMOS）堆叠芯片组件的嵌入式光电检测器装置。一个或多个变薄的CMOS层中的至少一个包括限定在一个或多个变薄的CMOS层内的有源光电二极管区域，有源光电二极管区域接收入射到其上的光信号，并且有源光电二极管区域包括减薄的CMOS层。体基板部分具有形成在其中的二极管光电检测器。

96. 发明授权

US07888959B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

97. 发明申请

US20110033952A1 Sensor for Biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US20110033952A1
公开(公告)日：2011-02-10
申请号：US12537063
申请日：2009-08-06
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/543 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.
摘要翻译：用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动当生物分子与抗体结合时，在源区和漏区之间变化。

98. 发明授权

US07067371B2 Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness 失效
标题翻译：绝缘体上硅（SOI）集成电路（IC）芯片，硅层由不同厚度的区域组成
公开(公告)号：US07067371B2
公开(公告)日：2006-06-27
申请号：US10900523
申请日：2004-07-28
申请人： Tak H. Ning , Devendra K. Sadana
发明人： Tak H. Ning , Devendra K. Sadana
IPC分类号： H01L21/8249
CPC分类号： H01L27/1203 , H01L21/84
摘要： The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.
摘要翻译：本发明提供SOI材料，其包括具有不同厚度的区域的顶部含Si层以及制造这种SOI材料的方法。本发明的方法包括通过硅的掩蔽氧化来稀释顶部含Si层的预定区域的步骤。还公开了包括具有不同类型的CMOS器件的本发明SOI材料的SOI IC芯片。

99. 发明授权

US5256896A Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor 失效
标题翻译：绝缘体上多晶硅 - 集电极 - 多晶硅 - 发射极双极晶体管
公开(公告)号：US5256896A
公开(公告)日：1993-10-26
申请号：US753278
申请日：1991-08-30
申请人： Tak H. Ning
发明人： Tak H. Ning
IPC分类号： H01L21/331 , H01L21/74 , H01L29/08 , H01L29/73 , H01L29/732 , H01L29/72
CPC分类号： H01L29/66272 , H01L21/74 , H01L29/0826 , H01L29/7317
摘要： A bipolar transistor is described having a thin subcollector formed from alternating polycrystalline semiconductor material and silicide material disposed over an insulating layer. Because the subcollector is thin the transistor is less sensitive to alpha-particle events. The transistor has enhanced inverse current gain since there is a polycrystalline contact to the inverse emitter.

100. 发明授权

US4688063A Dynamic ram cell with MOS trench capacitor in CMOS 失效
标题翻译：具有MOS沟槽电容器的动态RAM单元
公开(公告)号：US4688063A
公开(公告)日：1987-08-18
申请号：US920916
申请日：1986-10-21
申请人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
发明人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
IPC分类号： H01L27/108 , H01L29/94 , H01L29/78
CPC分类号： H01L27/10832 , H01L29/945
摘要： This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
摘要翻译：本发明一般涉及动态随机存取存储器（DRAM）单元，更具体地说，涉及一种DRAM单元，其中单元的存储电容器设置在形成于半导体衬底中的沟槽中。更具体地说，本发明涉及一种DRAM单元，其中基板的至少一部分被重掺杂并形成存储电容器的反电极，而设置在沟槽电容器中的重掺杂多晶硅形成存储电容器的另一个电极。 DRAM单元包括放置在与衬底的导电类型相反的阱中的场效应存取晶体管。阱本身形成在衬底的轻掺杂部分中，并且可以是n型或p型导电性，其中电池的其它部分具有适合于在CMOS环境中制造的器件的导电类型。沟槽电容器从阱的表面延伸穿过阱和轻掺杂衬底部分到衬底的重掺杂部分。设置在沟槽中的电极直接连接到存取晶体管的源极/漏极。

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