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91. 发明授权

US07543262B2 Analog layout module generator and method 有权
标题翻译：模拟布局模块发生器和方法
公开(公告)号：US07543262B2
公开(公告)日：2009-06-02
申请号：US11295268
申请日：2005-12-06
申请人： Zhigang Wang , Elias Fallon , Regis R. Colwell
发明人： Zhigang Wang , Elias Fallon , Regis R. Colwell
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
摘要翻译：在集成电路设计中的设备布局的计算机实现方法中，选择具有多个单元的阵列并将其存储在计算机的存储器中。在计算机的显示器上显示电路的多个互连电路装置的示意图。所显示的示意图的一个或多个电路装置由用户选择。响应于每个电路装置的选择，计算机的处理装置用电路装置的相应布局实例填充计算机的存储器中的阵列的空单元，其中每个布局实例表示材料的物理布置），形成相应的所选择的电路装置。

92. 发明授权

US07522453B1 Non-volatile memory with source-side column select 有权
标题翻译：源极列选择非易失性存储器
公开(公告)号：US07522453B1
公开(公告)日：2009-04-21
申请号：US11961134
申请日：2007-12-20
申请人： Zhigang Wang , Gregory Bakker , Volker Hecht , Santosh Yachareni , Fethi Dhaoui , Vidyadhara Bellippady
发明人： Zhigang Wang , Gregory Bakker , Volker Hecht , Santosh Yachareni , Fethi Dhaoui , Vidyadhara Bellippady
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/08
摘要： A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.
摘要翻译：非易失性存储器阵列段包括具有耦合到奇数源极线的漏极和耦合到偶数源极线的漏极的偶数选择晶体管的奇数选择晶体管。两个段选择晶体管具有耦合到奇数和偶数源极线的不同源极，耦合到地的源极和耦合到段选择线的栅极的漏极。多个奇数非易失性存储晶体管各自具有耦合到公共漏极线的漏极，耦合到奇数源极线的源极，浮动栅极和控制栅极。多个偶数非易失性存储晶体管每个都具有耦合到公共漏极线的漏极，耦合到偶数源极线的源极，浮动栅极和控制栅极。每个偶数非易失性存储晶体管的控制栅极耦合到奇数非易失性存储晶体管中不同一个的控制栅极。

93. 发明申请

US20090032723A1 Charged Particle Beam Irradiation System 有权
标题翻译：带电粒子束照射系统
公开(公告)号：US20090032723A1
公开(公告)日：2009-02-05
申请号：US12182709
申请日：2008-07-30
申请人： Ritsuo FUKAYA , Zhigang Wang
发明人： Ritsuo FUKAYA , Zhigang Wang
IPC分类号： H01J3/14
CPC分类号： H01J37/28 , H01J37/026 , H01J37/147 , H01J37/265 , H01J2237/0044
摘要： It is to prevent an image drift from occurring caused by a specimen being charged when observing the specimen including an insulating material.A first scan is performed in a predetermined direction on scanning line and in a predetermined sequential direction of scanning lines and a second scan is performed in a scanning direction different from the predetermined scanning direction and in a sequential direction different from the predetermined sequential direction. An image may be created by repeating the process of executing the second scan after executing the first scan and by requiring the arithmetic average of the frames obtained by the second scans. An image may be created by averaging arithmetically at least one frame obtained by the first scan and at least one frame obtained by the second scan.
摘要翻译：这是为了防止在观察包括绝缘材料的试样时由试样充电引起的图像漂移。在扫描线和扫描线的预定顺序方向上沿预定方向执行第一扫描，并且在与预定扫描方向不同的扫描方向上和沿与预定顺序方向不同的顺序方向上执行第二扫描。可以通过在执行第一次扫描之后重复执行第二扫描的处理并且要求通过第二扫描获得的帧的算术平均来创建图像。可以通过对由第一扫描获得的至少一帧和通过第二扫描获得的至少一帧进行算术平均来创建图像。

94. 发明授权

US07473960B1 Non-volatile two-transistor programmable logic cell and array layout 有权
标题翻译：非易失性双晶体管可编程逻辑单元和阵列布局
公开(公告)号：US07473960B1
公开(公告)日：2009-01-06
申请号：US11927265
申请日：2007-10-29
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

95. 发明申请

US20080093654A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 有权
标题翻译：非易失性双向晶体管可编程逻辑单元和阵列布局
公开(公告)号：US20080093654A1
公开(公告)日：2008-04-24
申请号：US11962615
申请日：2007-12-21
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

96. 发明申请

US20070276189A1 Rectal Expander 有权
标题翻译：直肠扩张器
公开(公告)号：US20070276189A1
公开(公告)日：2007-11-29
申请号：US10561649
申请日：2004-06-24
申请人： Eric Abel , James Hewit , Alan Slade , Zhigang Wang
发明人： Eric Abel , James Hewit , Alan Slade , Zhigang Wang
IPC分类号： A61B1/06 , A61B17/02
CPC分类号： A61B1/32 , A61B1/31 , A61M29/00
摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).
摘要翻译：公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12）），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

97. 发明授权

US07272060B1 Method, system, and circuit for performing a memory related operation 有权
标题翻译：用于执行存储器相关操作的方法，系统和电路
公开(公告)号：US07272060B1
公开(公告)日：2007-09-18
申请号：US11001940
申请日：2004-12-01
申请人： Qiang Lu , Richard Fastow , Zhigang Wang
发明人： Qiang Lu , Richard Fastow , Zhigang Wang
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/12
摘要： A method, system, and circuit for performing a memory related operation are disclosed. An operating voltage is applied to a bitline and a neighboring bitline is precharged. The precharge voltage has a magnitude less than the operating voltage. Both voltages ramp up at like or different rates. The precharge voltage can reach its effective magnitude prior to or with the operating voltage reaching its effective value.
摘要翻译：公开了一种用于执行存储器相关操作的方法，系统和电路。工作电压施加到位线，并且相邻位线被预充电。预充电电压的幅度小于工作电压。两个电压都以相同或不同的速率上升。预充电电压可以在工作电压达到其有效值之前或达到其有效幅度。

98. 发明授权

US07210082B1 Method for performing ATPG and fault simulation in a scan-based integrated circuit 有权
标题翻译：在基于扫描的集成电路中执行ATPG和故障模拟的方法
公开(公告)号：US07210082B1
公开(公告)日：2007-04-24
申请号：US11140579
申请日：2005-05-31
申请人： Khader S. Abdel-Hafez , Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Wang , Zhigang Jiang
发明人： Khader S. Abdel-Hafez , Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Wang , Zhigang Jiang
IPC分类号： G01R31/28 , G11B5/00 , G06F11/00
CPC分类号： G06F11/261 , G01R31/318307 , G01R31/318547
摘要： A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703, into a Sequential Circuit Model 705. The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707. The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation 710 are performed according to the Uncontrollable/Unobservable Labeling 709 to generate the HDL Test Benches and ATE Test Programs 711.
摘要翻译：一种在所选择的扫描测试模式或选定的自测模式中，基于所选择的捕获操作中所选择的时钟顺序，在基于扫描的集成电路中执行ATPG（自动测试模式生成）和故障模拟的方法。该方法包括将基于输入约束702和晶圆库703的RTL（寄存器传送级）或门级HDL（硬件描述语言）代码701编译成顺序电路模型705。然后将顺序电路模型705转换为等效的组合电路模型707，以执行前向和/或后向时钟分析708，以确定组合电路模型707中所有组合逻辑门的所有输入和输出的驱动和观察时钟。分析结果用于组合逻辑门的所选输入和输出的不可控/不可观察标签709。最后，ATPG和/或故障模拟710根据不可控/不可观察的标签709执行，以产生HDL测试台和ATE测试程序711。

99. 发明申请

US20070045539A1 Scanning electron microscope 有权
标题翻译：扫描电子显微镜
公开(公告)号：US20070045539A1
公开(公告)日：2007-03-01
申请号：US11509059
申请日：2006-08-24
申请人： Ritsuo Fukaya , Hidetoshi Sato , Zhigang Wang , Noriaki Arai , Makoto Ezumi
发明人： Ritsuo Fukaya , Hidetoshi Sato , Zhigang Wang , Noriaki Arai , Makoto Ezumi
IPC分类号： G21K7/00
CPC分类号： H01J37/28 , H01J2237/22
摘要： A scanning electron microscope is disclosed. The primary electron beam is radiated on a reticle (specimen), and an observation image of the reticle is obtained using the electrons secondarily released. The microscope comprises a lamp for radiating the vacuum ultraviolet light having the wavelength of not more than 172 nm on the reticle in the atmosphere, a radiation chamber for hermetically sealing the reticle so that the vacuum ultraviolet light can be radiated on the reticle, and a specimen holder for holding the reticle in the radiation chamber and capable of adjusting the distance between the lamp and the reticle.
摘要翻译：公开了一种扫描电子显微镜。将一次电子束照射在标线（样品）上，并使用二次释放的电子获得掩模版的观察图像。显微镜包括用于在大气中的掩模版上照射波长不大于172nm的真空紫外光的灯，用于气密地密封掩模版的辐射室，以便可以将真空紫外光照射在掩模版上，并且用于将掩模版保持在辐射室中并且能够调节灯和掩模版之间的距离的样本保持器。

100. 发明授权

US07151028B1 Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability 有权
标题翻译：具有等离子体生长氧化物间隔物的存储单元用于降低DIBL和Vss电阻并增加可靠性
公开(公告)号：US07151028B1
公开(公告)日：2006-12-19
申请号：US10981174
申请日：2004-11-04
申请人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
发明人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L21/26
CPC分类号： H01L29/66636 , H01L29/1037 , H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于基质。该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。

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