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91. 发明授权

US5559737A Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines 失效
标题翻译：非易失性半导体存储器能够同时均衡位线和感测线
公开(公告)号：US5559737A
公开(公告)日：1996-09-24
申请号：US338827
申请日：1994-11-10
申请人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
发明人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
IPC分类号： G11C17/00 , G11C7/12 , G11C16/06 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.
摘要翻译：在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管，主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件以及用于均衡感测线和虚拟细胞感测线的条件。因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

92. 发明授权

US5438542A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5438542A
公开(公告)日：1995-08-01
申请号：US332493
申请日：1994-10-31
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： H01L21/8247 , G11C16/08 , G11C16/30 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , H01L27/02
CPC分类号： G11C16/30 , G11C16/08 , H01L27/105
摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
摘要翻译：在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。外围晶体管TR形成在N型阱中。另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

93. 发明授权

US5262919A Semiconductor memory device including programming circuitry 失效
标题翻译：半导体存储器件包括编程电路
公开(公告)号：US5262919A
公开(公告)日：1993-11-16
申请号：US709825
申请日：1991-06-04
申请人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
发明人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/32 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/32 , G11C16/10
摘要： A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.

94. 发明授权

US5253201A Writing control circuit employed in non-volatile semiconductor memory device 失效
标题翻译：写入非易失性半导体存储器件中的控制电路
公开(公告)号：US5253201A
公开(公告)日：1993-10-12
申请号：US917953
申请日：1992-07-24
申请人： Shigeru Atsumi , Hironori Banba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C17/00 , G05F3/24 , G05F3/26 , G11C5/14 , G11C11/407 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/30 , G11C7/00
CPC分类号： G05F3/242 , G05F3/262 , G11C16/10 , G11C16/30 , G11C5/147
摘要： A write control circuit is provided for supplying a gate of an n-channel enhancement-type writing transistor with a voltage corresponding to data when the data is written. The circuit comprises a reference potential-generation circuit, a differential amplifier, and a feedback circuit. The reference potential-generation circuit generates a reference potential substantially equal to the upper limit of that high level of each of the bit lines which is assumed at the time of writing. The differential amplifier has an input terminal to be supplied with the reference potential. A write voltage serving as an operation voltage is applied to the amplifier. The feedback circuit is connected between the other input terminal and output terminal of the differential amplifier. The feedback circuit generates, under the control of the differential amplifier, a write control voltage higher than the reference potential by the threshold voltage of the writing transistor, and applies the write control voltage to the gate of the writing transistor. Also, the feedback circuit feeds a voltage obtained by reducing the write control voltage, back to the other input terminal of the differential amplifier.

95. 发明授权

US5233566A Address detector of a redundancy memory cell 失效
标题翻译：冗余存储单元的地址检测器
公开(公告)号：US5233566A
公开(公告)日：1993-08-03
申请号：US614140
申请日：1990-11-16
申请人： Keniti Imamiya , Shigeru Atsumi , Sumio Tanaka
发明人： Keniti Imamiya , Shigeru Atsumi , Sumio Tanaka
IPC分类号： G11C29/00 , G11C29/04 , G11C29/24 , H01L21/82 , H01L27/10
CPC分类号： G11C29/789 , G11C29/24
摘要： An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.
摘要翻译：提供冗余存储单元的地址检测器，其包括用于存储用于用冗余单元替换有缺陷单元的地址数据的编程元件。在测试模式中，冗余单元可被写入，而不管存储单元是否有缺陷。因此，可以对冗余单元进行测试，而不需要用冗余单元代替缺陷单元的编程元件。检测器还包括用于锁存编程元件的状态的锁存器和用于在测试模式下设置锁存器的数据设置元件。

96. 发明授权

US5105385A Cell array pattern layout for EEPROM device 失效
标题翻译： CELL ARRAY PATTERN LAYOUT FOR EEPROM DEVICE
公开(公告)号：US5105385A
公开(公告)日：1992-04-14
申请号：US703704
申请日：1991-05-21
申请人： Nobuaki Ohtsuka , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi
发明人： Nobuaki Ohtsuka , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi
IPC分类号： H01L21/8247 , G11C7/14 , G11C16/28 , H01L21/8246 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： G11C7/14 , G11C16/28
摘要： A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column. A dummy bit line is connected to the dummy capacitance cells and dummy memory cell, and a dummy word line is connected to the array edge memory cell and dummy memory cell.

97. 发明授权

US5046048A Semiconductor integrated circuit including output buffer 失效
标题翻译：半导体集成电路包括输出缓冲
公开(公告)号：US5046048A
公开(公告)日：1991-09-03
申请号：US379280
申请日：1989-07-13
申请人： Shigeru Atsumi , Sumio Tanaka , Junichi Miyamoto , Nobuaki Ohtsuka , Keniti Imamiya
发明人： Shigeru Atsumi , Sumio Tanaka , Junichi Miyamoto , Nobuaki Ohtsuka , Keniti Imamiya
IPC分类号： G01R31/317 , G06F11/00 , G11C7/10 , G11C29/34 , G11C29/46
CPC分类号： G11C7/1057 , G01R31/31701 , G06F11/00 , G11C29/34 , G11C29/46 , G11C7/1051
摘要： A semiconductor integrated circuit having a test mode in addition to a normal mode, includes a mode detecting circuit for detecting a state of each mode and generating a mode signal, a prebuffer circuit for receiving the mode signal generated by the mode detecting circuit, amplifying an input signal by using an output driving capacity corresponding to the mode signal, and outputting the amplified signal, and an output buffer circuit for receiving an output from the prebuffer circuit and outputting data outside the integrated circuit.

98. 发明授权

US4924339A Input protecting circuit in use with a MOS semiconductor device 失效
标题翻译： MOS半导体器件使用的输入保护电路
公开(公告)号：US4924339A
公开(公告)日：1990-05-08
申请号：US291476
申请日：1988-12-28
申请人： Shigeru Atsumi , Toru Yoshida , Yasuo Kawahara , Fuminari Tanaka
发明人： Shigeru Atsumi , Toru Yoshida , Yasuo Kawahara , Fuminari Tanaka
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H02H9/04
CPC分类号： H01L27/0251
摘要： A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

99. 发明授权

US4916665A Semiconductor memory device with P-channel MOS transistor load circuit 失效
标题翻译：具有P沟道MOS晶体管负载电路的半导体存储器件
公开(公告)号：US4916665A
公开(公告)日：1990-04-10
申请号：US610704
申请日：1984-05-16
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： G11C11/417 , G11C16/28
CPC分类号： G11C16/28
摘要： A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.
摘要翻译：本发明的半导体存储器件具有多个浮动栅极存储单元。检测器检测由解码器选择的存储在浮动栅极存储单元中的数据，并产生相应的检测信号。负载电路放大检测信号。放大的检测信号被提供给差分放大器。差分放大器将放大的检测信号的电压与参考电压发生器的参考电压进行比较，并产生与浮动栅极存储器中的存储内容相对应的二进制信号。负载电路是p沟道增强型MOS晶体管。负载晶体管具有栅极和漏极，其连接到检测器和差分放大器之间的节点，并且还具有接收预定电压的源极和衬底。

100. 发明授权

US4897815A High-speed write type nonvolatile semiconductor memory 失效
标题翻译：高速写型非易失性半导体存储器
公开(公告)号：US4897815A
公开(公告)日：1990-01-30
申请号：US96458
申请日：1987-09-15
申请人： Sumio Tanaka , Shinji Saito , Shigeru Atsumi , Nobuaki Ohtsuka
发明人： Sumio Tanaka , Shinji Saito , Shigeru Atsumi , Nobuaki Ohtsuka
IPC分类号： H01L21/8247 , G11C16/10 , H01L21/8246 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10
摘要： A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.
摘要翻译：通过将其中以矩阵形式提供EPROM单元的存储单元阵列和写入电路划分成多个块来获得本发明的非易失性半导体存储器，通常连接存储单元阵列的每个块中的单元晶体管的源极，并且通过相应的电阻分量将每个块的公共源连接到接地节点。

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