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91. 外观设计

USD549382S1 Light fitment 有权
标题翻译：轻装
公开(公告)号：USD549382S1
公开(公告)日：2007-08-21
申请号：US29237490
申请日：2005-09-01
申请人： Peter Lee
设计人： Peter Lee

92. 发明申请

US20070133289A1 NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same 审中-公开
标题翻译：具有高压PMOS和嵌入式多晶硅的NAND型闪存器件及其制造方法
公开(公告)号：US20070133289A1
公开(公告)日：2007-06-14
申请号：US11606535
申请日：2006-11-30
申请人： Han-Rei Ma , Fu-Chang Hsu , Peter Lee , Xiang Hong
发明人： Han-Rei Ma , Fu-Chang Hsu , Peter Lee , Xiang Hong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and −20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.
摘要翻译：本发明的器件包括形成在半导体衬底的预定区域并彼此平行延伸的多个隔离层。本发明的器件还包括放置在深N阱和NMOS顶部的高电压PMOS，其放置在外围区域的深N阱内的三重P阱上方，以通过周围的正和负高电压 + 20V和-20V到细胞区域。在一个实施例中，单元阵列，源极线和位线都被放置在P衬底的顶部上，而没有深N阱或三重P阱。在其他实施例中，将单元阵列，源极线和位线放置在深N阱和三重P阱的顶部。

93. 发明申请

US20060240490A1 Methods and compositions for identifying target cell cytolytic lymphocytes in a sample 审中-公开
标题翻译：用于鉴定样品中靶细胞溶细胞淋巴细胞的方法和组合物
公开(公告)号：US20060240490A1
公开(公告)日：2006-10-26
申请号：US11396349
申请日：2006-03-30
申请人： Peter Lee
发明人： Peter Lee
IPC分类号： G01N33/567 , G01N33/574
CPC分类号： G01N33/56972 , G01N2333/70517 , G01N2333/70596
摘要： Methods and compositions for identifying target cell cytolytic lymphocytes, e.g., T-cells, such as neoplastic cell cytolytic T-cells, in a subject are provided. In practicing the subject methods, the sample is contacted with a target cell stimulator, e.g., a neoplastic cell, and a detectably labeled granule membrane protein specific binding agent. Following contact, any resultant labeled lymphocytes, e.g., T-cells, are identified as lymphocytes cytolytic for the target cell. Also provided are compositions, kits, and systems for practicing the subject methods. The subject methods find use in a variety of different applications, including disease/therapy monitoring applications and therapeutic applications.
摘要翻译：提供了用于鉴定受试者中靶细胞溶细胞淋巴细胞如T细胞如肿瘤细胞溶细胞T细胞的方法和组合物。在实施本发明方法时，将样品与目标细胞刺激剂例如肿瘤细胞和可检测标记的颗粒膜蛋白特异性结合剂接触。在接触之后，任何得到的标记的淋巴细胞（例如T细胞）被鉴定为靶细胞溶细胞淋巴细胞。还提供了用于实践本发明方法的组合物，试剂盒和系统。主题方法可用于各种不同的应用，包括疾病/治疗监测应用和治疗应用。

94. 发明授权

US07123049B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US07123049B2
公开(公告)日：2006-10-17
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： H03K19/003
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

95. 发明申请

US20060144334A1 Method and apparatus for deposition of low dielectric constant materials 审中-公开
公开(公告)号：US20060144334A1
公开(公告)日：2006-07-06
申请号：US11369689
申请日：2006-03-07
申请人： Kang Yim , Soovo Sen , Dian Sugiarto , Peter Lee , Ellie Yieh
发明人： Kang Yim , Soovo Sen , Dian Sugiarto , Peter Lee , Ellie Yieh
IPC分类号： C23C16/00 , H01L21/20
CPC分类号： C23C16/45565 , C23C16/5096 , H01J37/32082 , H01J37/3244
摘要： A showerhead adapted for distributing gases into a process chamber and a method for forming dielectric layers on a substrate are generally provided. In one embodiment, a showerhead for distributing gases in a processing chamber includes an annular body coupled between a disk and a mounting flange. The disk has a plurality of holes formed therethrough. A lip extends from a side of the disk opposite the annular body and away from the mounting flange. The showerhead may be used for the deposition of dielectric materials on a substrate. In one embodiment, silicon nitride and silicon oxide layers are formed on the substrate without removing the substrate from a processing chamber utilizing the showerhead of the present invention.

96. 发明申请

US20060138245A1 Novel combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications 有权
标题翻译：用于多功能java卡，SIM卡，生物护照和生物识别卡应用的新型组合存储器设计和技术
公开(公告)号：US20060138245A1
公开(公告)日：2006-06-29
申请号：US11305700
申请日：2005-12-16
申请人： Peter Lee
发明人： Peter Lee
IPC分类号： G06K19/06
CPC分类号： G11C11/005 , G11C16/0408 , G11C16/0483 , G11C17/12 , H01L27/115 , H01L29/0646 , H01L29/7885
摘要： A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.
摘要翻译：易失性和非易失性存储器集成电路的组合具有放置在基板和多个非易失性存储器阵列上的至少一个易失性存储器阵列。易失性和非易失性存储器阵列具有彼此相关联的地址空间，使得每个阵列可以用公共寻址信号寻址。组合易失性和非易失性存储器集成电路还具有与外部电路通信的存储器控制电路，以接收地址，命令和数据信号。存储器控制电路解释地址，命令和数据信号，并且用于传送到易失性存储器阵列和用于读取，写入，编程和擦除易失性和非易失性存储器阵列的非易失性存储器阵列。易失性存储器阵列可以是SRAM，伪SRAM或DRAM。任何非易失性存储器阵列都可以屏蔽编程的ROM阵列，NAND配置闪存NAND配置的EEPROM。

97. 发明申请

US20060101552A1 Frictionally engaged supplied air helmet face seal 审中-公开
标题翻译：摩擦式供气头盔面罩
公开(公告)号：US20060101552A1
公开(公告)日：2006-05-18
申请号：US10988789
申请日：2004-11-15
申请人： Peter Lee , Desmond Curran , Richard Williams
发明人： Peter Lee , Desmond Curran , Richard Williams
IPC分类号： A41D13/00
CPC分类号： A62B18/082 , A62B18/04
摘要： A supplied air helmet 10 that has a visor 14, and a face seal 12 that includes a frame member 16 and a sealing member 18. The frame member 116 can be secured to the visor 14 by frictional engagement. The use of frictional engagement as opposed to pegs, adhesives, and hook and look type fasteners, may reduce the number of parts, may permit face seal installation and/or removal in a less onerous manner, and may reduce the opportunity for fastener failure.
摘要翻译：具有遮阳板14的供气头盔10和包括框架构件16和密封构件18的面密封件12。框架构件116可以通过摩擦接合固定到遮阳板14上。使用摩擦接合而不是栓钉，粘合剂和挂钩和外观类型的紧固件可以减少部件的数量，可以以较不繁重的方式安装和/或移除面部密封件，并且可以减少紧固件失效的机会。

98. 发明申请

US20060061512A1 Antennas encapsulated within plastic display covers of computing devices 有权
标题翻译：封装在计算设备的塑料显示盖内的天线
公开(公告)号：US20060061512A1
公开(公告)日：2006-03-23
申请号：US10946868
申请日：2004-09-22
申请人： Takeshi Asano , Shohhei Fujio , Brian Gaucher , Peter Lee , Duixian Liu , Kazuo Masuda , Hideyuki Usui , Osamu Yamamoto
发明人： Takeshi Asano , Shohhei Fujio , Brian Gaucher , Peter Lee , Duixian Liu , Kazuo Masuda , Hideyuki Usui , Osamu Yamamoto
IPC分类号： H01Q1/24
CPC分类号： H01Q1/2266 , G06F1/1616 , G06F1/1637 , G06F1/1698 , H01Q1/22 , H01Q1/40 , H01Q7/00 , H01Q9/16 , H01Q9/42
摘要： Antenna devices are provided comprising antenna structures encapsulated or molded into plastic covers of computing devices to enable wireless communication. For example, one or more antenna structures can be encasulated within, or molded into, a plastic display cover of a portable laptop computer. Embedded antenna designs can include various antenna types that are built using one or more wires or thin metallic strips encapsulated into plastic device covers. Insert/injection molding methods can be used to encapsulate antenna structures in plastic device covers during fabrication of the plastic device covers.
摘要翻译：提供了天线装置，其包括封装或模制成计算装置的塑料盖的天线结构以实现无线通信。例如，一个或多个天线结构可以被封装在便携式膝上型计算机的塑料显示器盖内或模制在其中。嵌入式天线设计可以包括使用一个或多个电线或薄的金属条封装在塑料器件盖中构建的各种天线类型。在塑料装置盖的制造期间，可以使用插入/注射成型方法将天线结构封装在塑料装置盖中。

99. 发明申请

US20060057659A1 Destructible surfactants and uses thereof 有权
公开(公告)号：US20060057659A1
公开(公告)日：2006-03-16
申请号：US10516418
申请日：2003-05-30
申请人： Edouard Bouvier , Bruce Compton , John Gebler , Martin Gilar , Ying-Qing Yu , Peter Lee , Elizabeth Brown
发明人： Edouard Bouvier , Bruce Compton , John Gebler , Martin Gilar , Ying-Qing Yu , Peter Lee , Elizabeth Brown
IPC分类号： C12Q1/37
CPC分类号： C12Q1/37 , C12P21/06 , G01N27/44726 , G01N27/44747 , G01N33/5306
摘要： The present invention provides methods for enhancing chemical reactions of molecules, e.g., biomolecules, with destructible surfactants. The chemical reactions may involve and/or be associate with analysis, e.g., solubilizing, separating, purifying and/or characterizing the molecules. In one aspect, the anionic surfactants of the present invention may be selectively broken up at relatively low pH. The resulting breakdown products of the surfactants may be removed from the molecule/sample with relative ease. The invention has applicability in a variety of analytical techniques.

100. 发明申请

US20060023503A1 Novel NVRAM memory cell architecture that integrates conventional SRAM and flash cells 失效
标题翻译：新型NVRAM存储单元架构，集成了常规SRAM和闪存单元
公开(公告)号：US20060023503A1
公开(公告)日：2006-02-02
申请号：US11056901
申请日：2005-02-11
申请人： Peter Lee
发明人： Peter Lee
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C14/0063 , G11C14/00 , G11C16/10
摘要： A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element in communication first and second nonvolatile memory elements to receive and permanently retain the digital signal from the latched memory element. A power detection circuit detects a power interruption and a power initiation and communicates the detection of the power interruption and power initiation to the plurality of integrated nonvolatile SRAM circuits. The SRAM cell, upon detection of the power interruption, transmits the digital signal to the first and second nonvolatile memory elements. The SRAM cell of each of the nonvolatile static random access memories upon detection of the power initiation, receives the digital signal from the first and second nonvolatile memory elements.
摘要翻译：非易失性SRAM阵列具有在基板上以行和列布置的集成非易失性SRAM电路阵列。每个集成的非易失性SRAM电路包括SRAM单元，第一和第二非易失性存储元件。 SRAM单元在通信第一和第二非易失性存储器元件中具有锁存的存储器元件，用于接收并永久地保持来自锁存的存储器元件的数字信号。电力检测电路检测电力中断和电力启动，并将电力中断和电力启动的检测传送到多个集成的非易失性SRAM电路。 SRAM单元在检测到电源中断时将数字信号发送到第一和第二非易失性存储器元件。在检测到功率启动时，每个非易失性静态随机存取存储器的SRAM单元接收来自第一和第二非易失性存储器元件的数字信号。

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